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lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
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HOW to implement benchmarks with pack array inernal signal #1176

Open anhdv2000 opened 1 year ago

anhdv2000 commented 1 year ago

I tried implementing benchmarks with the pack array signal but failed at the yosys stage. Tell me have you tried with such RTL ? and how to solve

as far as i know yosys can't read RTL with pack signal

tangxifan commented 1 year ago

@anhdv2000 Can you detail what is the pack array signal? We do have some example about carry chain mapping through yosys.

https://github.com/lnis-uofu/OpenFPGA/blob/master/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf