Problem with flipflop architecture

[Nguyenthehuy1]

I have written my own flipflop architecture (it includes posedge clk - posedge reset - posedge set - active HIGH and posedge clk - posedge reset - posedge set - active LOW), I defined two modules in "openfpga_dff_sim.v" -> in the "ff_test_2.blif" file, I saw two architectures with the same name: “_DFFPPP”.

I wonder how open FPGA can understand that two flip-flop architecture.

[tangxifan]

@Nguyenthehuy1 If you see the DFF_PPP in your blif file. It means that Yosys failed to do technology mapping for some DFFs in your RTL design. I suggest to double check your dff mapping rules. For example:

https://github.com/lnis-uofu/OpenFPGA/blob/master/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v

[Nguyenthehuy1]

Assume that " Yosys success to do technology mapping for some DFFs in my RTL design"DFF_PPP" is true and this process generate the name "DFF_PPP" (or other names), how can I distinguish two above flipflop architectures with the same name (DFF_PPP)?

[tangxifan]

@Nguyenthehuy1 I believe Yosys documentation provides detailed explanation. The DFF_PPP is an internal DFF type of Yosys. If tech map failed, Yosys just write out the internal FF. Then you see errors in VPR.