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lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
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SDC File generation paths are broken #1389

Open nachiket opened 11 months ago

nachiket commented 11 months ago

SDC files generated by OpenFPGA have buggy Verilog module hierarchy paths. I had a makeshift script to fixup the paths but it seems to have gotten worse, unless I'm doing things wrongly.

I run the following:

python3 $OPENFPGA_ROOT/openfpga_flow/scripts/run_fpga_task.py synthesized_verilog

The task.conf here uses k6_N10_tileable_40nm.xml, openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga, and a 2x2 FPGA with W=20

For example, for a simple 2x2 FPGA design, I wrote a synthesis TCL that includes a bunch of SDC import.

read_sdc $env(RTLDIR)/SDC/disable_sb_outputs.sdc

Reading SDC version 2.1...
Warning: Can't find object 'sb_0__1_/sb_0__2_/chany_top_out' in design 'fpga_top'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'sb_0__1_/sb_0__2_/chanx_right_out' in design 'fpga_top'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'sb_0__1_/sb_0__2_/chany_bottom_out' in design 'fpga_top'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'sb_0__1_/sb_0__2_/ccff_tail' in design 'fpga_top'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'sb_0__1_/sb_0__2_/sb_0__3_/chany_top_out' in design 'fpga_top'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'sb_0__1_/sb_0__2_/sb_0__3_/chanx_right_out' in design 'fpga_top'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'sb_0__1_/sb_0__2_/sb_0__3_/chany_bottom_out' in design 'fpga_top'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'sb_0__1_/sb_0__2_/sb_0__3_/ccff_tail' in design 'fpga_top'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'sb_1__0_/sb_2__0_/chany_top_out' in design 'fpga_top'. (UID-95)

I check the SDC file

$ cat $RTLDIR/SDC/disable_sb_outputs.sdc
set_disable_timing sb_0__0_/chany_top_out

set_disable_timing sb_0__0_/chanx_right_out

set_disable_timing sb_0__0_/ccff_tail

set_disable_timing sb_0__1_/chany_top_out

set_disable_timing sb_0__1_/chanx_right_out

set_disable_timing sb_0__1_/chany_bottom_out

set_disable_timing sb_0__1_/ccff_tail

set_disable_timing sb_0__1_/sb_0__2_/chany_top_out
...

Note the last weird string "sb_01_/sb_02_/chany_top_out" which should really be "sb_0_2/chany_top_out". This happens extensively in all generated SDC files.

Is there any suggestions for where we could look to start debugging this?

tangxifan commented 11 months ago

@nachiket The SDC generator has been out-of-date for a while. Currently, our focus is on improving the netlist and testbench generators. Afterwards, we will fix the bugs on SDC. My suggestion is to check the SDC files and adapt for your needs for now.

Similar problem has already been stated in other issue #784 . We are aware of the bugs and will try to fix it the earliest we can.