Routing Optimizations

[msaideroglu]

I'm running a basic and2 benchmark with basic full_testbench task on K4N4 and K4_frac_N4 architectures that OpenFPGA repo includes. However I'm seeing different routing results when I check VPR visualizations. I'm sharing the screenshot below. At the left side and2 routed very well on K4N4 but at the right side there are a huge routing path for the same circuit on K4_frac_N4. How should we interpret this? Is it possible to optimize routing more? Thanks.

[tangxifan]

What could happen is that routing arch is different in the two cases. To optimize routing architecture, you may look into all the options and parameters available in VPR architecture and tileable routing architecture.

[msaideroglu]

This is related part of k4_frac_N4_tileable_40nm.xml:

<device>
    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
          area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
      -->
    <area grid_logic_tile_area="0"/>
    <chan_width_distr>
      <x distr="uniform" peak="1.000000"/>
      <y distr="uniform" peak="1.000000"/>
    </chan_width_distr>
    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
    <connection_block input_switch_name="ipin_cblock"/>
  </device>
  <switchlist>
    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
  </switchlist>
  <segmentlist>
    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
      <mux name="0"/>
      <sb type="pattern">1 1 1 1 1</sb>
      <cb type="pattern">1 1 1 1</cb>
    </segment>
  </segmentlist>

This one is for k4_N4_tileable.xml:

<device>
    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
          area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
      -->
    <area grid_logic_tile_area="0"/>
    <chan_width_distr>
      <x distr="uniform" peak="1.000000"/>
      <y distr="uniform" peak="1.000000"/>
    </chan_width_distr>
    <switch_block type="wilton" fs="3"/>
    <connection_block input_switch_name="ipin_cblock"/>
  </device>
  <switchlist>
    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
  </switchlist>
  <segmentlist>
    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
      <mux name="0"/>
      <sb type="pattern">1 1 1 1 1</sb>
      <cb type="pattern">1 1 1 1</cb>
    </segment>
  </segmentlist>

[msaideroglu]

There is a little difference in k4_frac_N4: <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/> k4_N4: <switch_block type="wilton" fs="3"/>

[msaideroglu]

Could CLB input output positions be the reason for this result? I kept them with spread option both.

[tangxifan]

@msaideroglu

The difference in switch block will definitely create the difference. If you do not touch your CLB arch, the spread option does not impact your routing.