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lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
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Bitstream WL incremental/decremental option is broken #1466

Closed chungshien closed 9 months ago

chungshien commented 9 months ago

Describe the bug A clear and concise description of what the bug is.

The bitstream WL sequence (can be WL incremental or decremental control via the option) is broken because of commit of https://github.com/lnis-uofu/OpenFPGA/commit/1e8bf1ceceefdaf5c5a93339e82658656a5b659e#diff-039f23a060209f5dafc8ce53956898ff6a954849c7cd96df3b71b85cd7735561L132-L137

chungshien commented 9 months ago

I will fix this

@alain-rs @alaindargelas

alaindargelas commented 9 months ago

@chungshien , also maybe a test was missing, so that commit broke the functionality without any apparent failure. Please add explicit test(s).

chungshien commented 9 months ago

@alaindargelas

From bitstream file itself (or OpenFPGA), whatever WL ordering (incremental, decremental or even randomness) is, it does not matter, they are all a valid bitstream as long as the bit set is correct. This is because both BL and WL were specified in same line of the bitstream.

It is all about the reader of the bitstream.

The QL Memory Bank configuration tests are already there, but the test does not care WL order (which from the correctness of bitstream perspective, it is fine), I will see what I can do to enhance the test to make sure WL must be in certain order.