Clock Network Architecture

[mustafaarslan0]

I am researching clock network architectures of commercial FPGAs for a while and I see FPGAs can have multiple external clock inputs, PLLs, clock gating cells etc.. Also clock networks can be driven from internal logic.

Currently, the clock routing done by OpenFPGA Repack. So VPR does not know which clock input should be used. OpenFPGA Repack is not sufficient way to do complex clock routing. So I think clock routing should be done by VPR to provide:

• choosing the appropriate clock among many clocks,
• routing clock crossingly PLLs and clock gating cells,
• driving clock network from internal logic,
• selecting clock with internal logic select signal.

Actually, I do not know what to do. But I think improving current VPR Clock Architecture and binding it to OpenFPGA fabric is more accurate way to do it beside current solution. I see similar subject is discussed in issue #1311 and I want to continue discussion of the clock network architecture.

Thanks.

[mustafaarslan0]

Currently I use repack_constraints without clock network. It works fine so far.