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lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
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ql_memory_bank reading bitstream back #1503

Open mustafaarslan0 opened 8 months ago

mustafaarslan0 commented 8 months ago

I use ql_memory_bank shift_register configuration protocol with SRAM cells. SRAM cells have BL, WL and WLR pins as described in OpenFPGA Circuit model examples.

We need read enable signal for reading SRAM but I think WLR is overkill for this function. Wouldn't it be better if we use 1-bit wide read_enable signal (connected to all SRAMs) and WL together. WL is for decoding and read_enable signal is for deciding write or read operation.

Also BL should be defined as inout for bidirectional read/write operations.

Thank you, Best regards.

tangxifan commented 8 months ago

@mustafaarslan0

In your case, you may consider to create a global signal EN for your SRAM. Take the example (focus on the CFG_EN port)

https://openfpga.readthedocs.io/en/master/manual/arch_lang/circuit_model_examples/#configuration-chain-flip-flop-with-configure-enable-signals

mustafaarslan0 commented 5 months ago

@tangxifan creating a global EN signal works. But BL should be defined as inout for bidirectional read/write operations.