Support Existing Tape-outs in Regression Tests

[tangxifan]

Is your feature request related to a problem? Please describe. There have been several tape-out completed by using OpenFPGA. For example, the SOFA series. To keep a constant support on these tape-outs, OpenFPGA's regression tests should test bitstream generation and HDL simulation on existing netlists.

However, current regression tests only focus on a complete flow: netlist generation -> bitstream/testbench generation -> HDL simulation. This may cause a tape-out to be disconnected from the OpenFPGA support:

• Any changes on netlist generator will cause a change on bitstream generator
• A complete flow is always working as the generators are geared well internally
• A tape-out has a harden netlist which may not work when netlist generator is upgraded.

Describe the solution you'd like There is a strong to upgrade the OpenFPGA flow scripts to

• Take an existing netlist (could from post-PnR netlist)
• Generate bitstream and testbenches using the architecture description files (used to build the tape-out)
• Run HDL simulation to ensure functional correctness

[tangxifan]

@ganeshgore I think this is well needed as we have a number of tape-outs done. I would like to see it happen soon. @yashton If you have time, we can work together on these scripts. Currently, our regression tests are still too simple.