Repack failure for nets with multiple destinations within a complex block.

[Crossbomber]

Which part of OpenFPGA is buggy

[ X ] FPGA-Bitstream / Repack

Describe the bug During repack, nets which start at the output of a primitive inside of a complex block (e.g. a LUT output) but have multiple destinations (e.g. the signal is both routed to the input of the flipflop and the output of the CLB) are added to the routed nets during repacking twice. This results in a failure, since the repacker thinks a Pin is overused. See following snippet from the log:

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Pb route for Net d:
Source node:
    clb[0]/fle[3]/ble4[0]/ff[0].Q[0] -> clb[0]/fle[3]/ble4[0]/ff[0].Q[0]
Sink nodes:
    clb[0].O[6]
Pb route for Net c:
Source node:
    clb[0]/fle[3]/ble4[0]/lut4[0].out[0] -> clb[0]/fle[3]/ble4[0]/lut4[0].out[0]
Sink nodes:
    clb[0]/fle[3]/ble4[0]/ff[0].D[0]
    clb[0].O[7]
Pb route for Net c:
Source node:
    clb[0]/fle[3]/ble4[0]/lut4[0].out[0] -> clb[0]/fle[3]/ble4[0]/lut4[0].out[0]
Sink nodes:
    clb[0]/fle[3]/ble4[0]/ff[0].D[0]
    clb[0].O[7]
Added 6 nets to be routed.
Route failed due to overuse pin 'clb[0].O[7]': occupancy '2' > capacity '1'!
Route failed due to overuse pin 'clb[0].O[7]': occupancy '2' > capacity '1'!
Route failed due to overuse pin 'clb[0].O[7]': occupancy '2' > capacity '1'!
Route failed due to overuse pin 'clb[0].O[7]': occupancy '2' > capacity '1'!
Route failed due to overuse pin 'clb[0].O[7]': occupancy '2' > capacity '1'!
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As you can see, the net c is added to be routed twice. This results in the overuse pin error.

I have prepared a zip file (repack_bug.zip) with an example task to reproduce the error. In the zip file, you also find an edited repack.cpp file, which fixes this error. Since I'm not very familiar with the code base this fix may be a bit "hacky". You can implement it as is or employ a better fix. In my tests, this bug only occurs for nets, of which the sourcepin is within the complex block. If the sourcepin is an input pin of the block, repack seems to work fine.

To Reproduce Steps to reproduce the behavior:

1. Clone OpenFPGA repository and checkout latest / any fairly recent commit
2. Execute OpenFPGA task provided in the zip-file above

3. See error

   Expected behavior Repack should succeed and generate a valid bitstream.

   Enviornment:

   • OS:
   • [ X ] Ubuntu 20.04 (Running on a VM) --->
   • Compiler:
   • [ X ] gcc-9 (9.4.0)
   • Version:
   • [ X ] Current master

[tangxifan]

@Crossbomber It makes sense to me, feel free to create a PR.