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lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
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Fabric that fits input RTL #1642

Closed findnabeel closed 6 months ago

findnabeel commented 6 months ago

With openfpga, is there a way to get a required fabric corresponding to a given RTL design?. In other words, my tool input will be a verilog design and tool should output fpga fabric that can fit the input design.

tangxifan commented 6 months ago

@findnabeel You can just enable auto-sizing when calling vpr in OpenFPGA. Then it will give the smallest fabric which can accommodate your RTL design. See the following example:

https://github.com/lnis-uofu/OpenFPGA/blob/fddb700d7b55a616c643db7fc99e281fc56cc7d8/openfpga_flow/openfpga_shell_scripts/example_script.openfpga#L3