Open PradyumnaG opened 2 months ago
@PradyumnaG The root of the cause is that pin location should be well considered when you define a tile whose height/width is larger than 1. To ensure every pin can be accessed by routing tracks, there are two choices:
perimeter
pattern for pin location: https://docs.verilogtorouting.org/en/latest/arch/reference/#tag-%3Cpinlocationspattern=
I'm facing an issue for an ADDER custom pb_type.
The error is: [ -1.7e-09: -1.Error 1: in check_rr_graph: node 1080 (IPIN) at (2,2) block=ADDER1 side=BOTTOM pin=ADDER1.b[29] has no fanin. Error 2: in check_rr_graph: node 1081 (IPIN) at (2,2) block=ADDER1 side=BOTTOM pin=ADDER1.b[30] has no fanin. Error 3: in check_rr_graph: node 1082 (IPIN) at (2,2) block=ADDER1 side=BOTTOM pin=ADDER1.b[31] has no fanin. Error 4: in check_rr_graph: node 1112 (IPIN) at (2,2) block=ADDER1 side=LEFT pin=ADDER1.a[29] has no fanin. Error 5: in check_rr_graph: node 1113 (IPIN) at (2,2) block=ADDER1 side=LEFT pin=ADDER1.a[30] has no fanin. Error 6: in check_rr_graph: node 1114 (IPIN) at (2,2) block=ADDER1 side=LEFT pin=ADDER1.a[31] has no fanin. -11
The below is the ADDER tile:
openfpgashell.log k6_N10_40nm_copy_open.txt k6_N10_40nm_openfpga_proj.txt I have uploaded the files, can you help me out?