search

lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
813 stars 161 forks source link

Support little-endian convention for the verilog netlist #250

Open ganeshgore opened 3 years ago

ganeshgore commented 3 years ago

Is your feature request related to a problem? Please describe. Currently OpenFPGA generated Verilog netlist used big-endian convention, which is not most conventional way. Extra care needs to be taken while interfacing the signal on the GPIOs.

Describe the solution you'd like Prefer little-endian convention for the netlist, atleast for the top level signals.

tangxifan commented 3 years ago

@ganeshgore Action item: I will create a branch for this feature. We will work on that branch