A complete end-to-end walkthrough

[manili]

Hi all, I'm completely getting lost through the tutorials and "full documentation". I really did not know where to request for help except here. (so I'm very sorry if this issue is not like a real issue at all.) OK, what I want to do is creating an iCE40-like FPGA for my self, see its final Verilog netlist and finally create Verilog to SPICE and GDSII outputs. Then write a simple code for this custom FPGA and compile it via OpenFPGA toolchain. So now the question is where should I start and how should I go step by step and see the results?

P.S. I think the lack of a complete and sample-based tutorial for the framework is a big problem for the newbies like me.

Best regards, Manili

[tangxifan]

@manili The task you mentioned is actually what a FPGA company should do. It requires a lot of efforts. It means the learning curve may be very steep. You need to pick up a lot of background knowledges.

• The VTR documentation about architecture description language should be studied, through which you learn how to model an FPGA architecture
• The OpenFPGA architecture description language should be studied, through which you learn how to build an FPGA fabric
• Afterwards, I suggest to read the tutorial about how to verify FPGA fabric.

[tomBGU]

Hello all (@tangxifan ), I'm using this thread since my questions are not actual implementation issues, hope its fine.

Is the proposed workflow and provided software restricted to specific fabrication processes? Can the final fabric be implemented within a SoC (as an eFPGA and not as a stand-alone FPGA)? Can you reference publications that describe or showcase the implementation or utilization of the proposed methodology and tools?

Thanks in advance, Tom

[manili]

Hi all, Seems like the VSD has a good virtual workshop around OSFPGA. I highly recommend everyone to check it out: https://www.vlsisystemdesign.com/fpga