Cannot find the model for subcircuit

[Chloe123Jackson]

I have been trying to create a .act file for a .blif file of my own, but it shows the following error:

Line 10: Cannot find the model for subcircuit NOT. Reading network from file has failed. /home/user/OpenFPGA/ace2/SRC/ace.c:357 main: Assertion 'ntk' failed.

I'm not sure how to fix it. It would be helpful to get an insight on the same.

[tangxifan]

Hi @Chloe123Jackson , there could be various reasons why ACE failed. Would you mind sharing your .blif file? According to what you say Cannot find the model for subcircuit NOT, it seems that your BLIF file contains subcircuit .model other than the LUTs .names and FFs .latch.

[Chloe123Jackson]

Yeah sure. The blif file has been provided below:

Generated by Yosys 0.9+2406 (git sha1 f44a4f90, gcc 9.3.0-17)

.model Slice .inputs FXINA FXINB BY Clk CE BX Clr FLUT_sel[0] FLUT_sel[1] FLUT_sel[2] FLUT_sel[3] GLUT_sel[0] GLUT_sel[1] GLUT_sel[2] GLUT_sel[3] FLUT_ram[0] FLUT_ram[1] FLUT_ram[2] FLUT_ram[3] FLUT_ram[4] FLUT_ram[5] FLUT_ram[6] FLUT_ram[7] FLUT_ram[8] FLUT_ram[9] FLUT_ram[10] FLUT_ram[11] FLUT_ram[12] FLUT_ram[13] FLUT_ram[14] FLUT_ram[15] GLUT_ram[0] GLUT_ram[1] GLUT_ram[2] GLUT_ram[3] GLUT_ram[4] GLUT_ram[5] GLUT_ram[6] GLUT_ram[7] GLUT_ram[8] GLUT_ram[9] GLUT_ram[10] GLUT_ram[11] GLUT_ram[12] GLUT_ram[13] GLUT_ram[14] GLUT_ram[15] FLUT_we GLUT_we GYMUX_sel DYMUX_sel FXMUX_sel DXMUX_sel .outputs Fi Y YQ F5 X XQ .names $false .names $true 1 .names $undef .subckt NOT A=GYMUX_sel Y=$abc$151$newn21 .subckt NOT A=DYMUX_sel Y=$abc$151$newn22 .subckt NOT A=BX Y=$abc$151$newn23 .subckt NOT A=FXMUX_sel Y=$abc$151$newn24 .subckt NOT A=DXMUX_sel Y=$abc$151$newn25 .subckt NOT A=FXINB Y=$abc$151$newn26 .subckt NOT A=GLUT_out Y=$abc$151$newn27 .subckt NOT A=FLUT_out Y=$abc$151$newn28 .subckt NAND A=BY B=FXINA Y=$abc$151$newn29 .subckt NOT A=$abc$151$newn29 Y=$abc$151$newn30 .subckt NOR A=BY B=$abc$151$newn26 Y=$abc$151$newn31 .subckt NOR A=$abc$151$newn30 B=$abc$151$newn31 Y=$abc$151$newn32 .subckt NOT A=$abc$151$newn32 Y=Fi .subckt NOR A=$abc$151$newn24 B=$abc$151$newn32 Y=$abc$151$newn34 .subckt NOR A=FXMUX_sel B=$abc$151$newn28 Y=$abc$151$newn35 .subckt NOR A=$abc$151$newn34 B=$abc$151$newn35 Y=$abc$151$newn36 .subckt NOT A=$abc$151$newn36 Y=X .subckt NOR A=$abc$151$newn25 B=$abc$151$newn36 Y=$abc$151$newn38 .subckt NAND A=BX B=$abc$151$newn25 Y=$abc$151$newn39 .subckt NAND A=CE B=$abc$151$newn39 Y=$abc$151$newn40 .subckt NOR A=$abc$151$newn38 B=$abc$151$newn40 Y=$abc$151$newn41 .subckt NOR A=CE B=XQ Y=$abc$151$newn42 .subckt NOT A=$abc$151$newn42 Y=$abc$151$newn43 .subckt NAND A=Clr B=$abc$151$newn43 Y=$abc$151$newn44 .subckt NOR A=$abc$151$newn41 B=$abc$151$newn44 Y=$0\XQ[0:0] .subckt NOR A=$abc$151$newn21 B=$abc$151$newn32 Y=$abc$151$newn46 .subckt NOR A=GYMUX_sel B=$abc$151$newn27 Y=$abc$151$newn47 .subckt NOR A=$abc$151$newn46 B=$abc$151$newn47 Y=$abc$151$newn48 .subckt NOT A=$abc$151$newn48 Y=Y .subckt NOR A=$abc$151$newn22 B=$abc$151$newn48 Y=$abc$151$newn50 .subckt NAND A=BY B=$abc$151$newn22 Y=$abc$151$newn51 .subckt NAND A=CE B=$abc$151$newn51 Y=$abc$151$newn52 .subckt NOR A=$abc$151$newn50 B=$abc$151$newn52 Y=$abc$151$newn53 .subckt NOR A=YQ B=CE Y=$abc$151$newn54 .subckt NOT A=$abc$151$newn54 Y=$abc$151$newn55 .subckt NAND A=Clr B=$abc$151$newn55 Y=$abc$151$newn56 .subckt NOR A=$abc$151$newn53 B=$abc$151$newn56 Y=$0\YQ[0:0] .subckt NAND A=BX B=GLUT_out Y=$abc$151$newn58 .subckt NAND A=$abc$151$newn23 B=FLUT_out Y=$abc$151$newn59 .subckt NAND A=$abc$151$newn58 B=$abc$151$newn59 Y=F5 .subckt DFF C=Clk D=$0\XQ[0:0] Q=XQ .subckt DFF C=Clk D=$0\YQ[0:0] Q=YQ .subckt lut_4 clk=Clk lut_out=FLUT_out lut_sel[0]=FLUT_sel[0] lut_sel[1]=FLUT_sel[1] lut_sel[2]=FLUT_sel[2] lut_sel[3]=FLUT_sel[3] ram_i[0]=FLUT_ram[0] ram_i[1]=FLUT_ram[1] ram_i[2]=FLUT_ram[2] ram_i[3]=FLUT_ram[3] ram_i[4]=FLUT_ram[4] ram_i[5]=FLUT_ram[5] ram_i[6]=FLUT_ram[6] ram_i[7]=FLUT_ram[7] ram_i[8]=FLUT_ram[8] ram_i[9]=FLUT_ram[9] ram_i[10]=FLUT_ram[10] ram_i[11]=FLUT_ram[11] ram_i[12]=FLUT_ram[12] ram_i[13]=FLUT_ram[13] ram_i[14]=FLUT_ram[14] ram_i[15]=FLUT_ram[15] we=FLUT_we .subckt lut_4 clk=Clk lut_out=GLUT_out lut_sel[0]=GLUT_sel[0] lut_sel[1]=GLUT_sel[1] lut_sel[2]=GLUT_sel[2] lut_sel[3]=GLUT_sel[3] ram_i[0]=GLUT_ram[0] ram_i[1]=GLUT_ram[1] ram_i[2]=GLUT_ram[2] ram_i[3]=GLUT_ram[3] ram_i[4]=GLUT_ram[4] ram_i[5]=GLUT_ram[5] ram_i[6]=GLUT_ram[6] ram_i[7]=GLUT_ram[7] ram_i[8]=GLUT_ram[8] ram_i[9]=GLUT_ram[9] ram_i[10]=GLUT_ram[10] ram_i[11]=GLUT_ram[11] ram_i[12]=GLUT_ram[12] ram_i[13]=GLUT_ram[13] ram_i[14]=GLUT_ram[14] ram_i[15]=GLUT_ram[15] we=GLUT_we .end

[tangxifan]

@Chloe123Jackson This is because in the .blif file, the model of NOT, NAND, DFF, lut_4are not defined. You need to define them at the end of the.blif`` file. For example,

.model DFF
.inputs C D
.outputs Q

[Chloe123Jackson]

@tangxifan It worked . Thank you for the help.

[tangxifan]

@Chloe123Jackson No worries. Feel free to contact whenever you see an issue. If you do not mind, I will close this issue.