Autocheck Simulation Early Termination

[lukefahr]

Describe the bug

It looks like if I set up a task with the following in the config/task.conf:

[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

Then OpenFPGA generates the following for a define_simulation.v:

//----- Time scale -----
`timescale 1ns / 1ps

`define ICARUS_SIMULATOR 1

`define AUTOCHECKED_SIMULATION 1

`define ENABLE_FORMAL_VERIFICATION 1

`define FORMAL_SIMULATION 1

When VVP is run, it will simultaneously simulate both the autocheck and the formal testbenches. Whichever one calls $finish first ( usually top_formal) will terminate the simulation. However, the longer-running testbench ( autocheck) is terminated prematurely.

Is this intended behavior?

[tangxifan]

@lukefahr

When you write the following lines, it means you want to run preconfigured testbenches.

[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

The openfpga_flow python script will modify the define_simulation.v where some flags are removed so that you can run HDL simulations. You can check in our your local run directory. There is a define_simulation.v.bak file which keeps the original copy. As such, even if your openfpga shell script enabled both full testbench and preconfigured testbenches, the HDL simulations will not break.

Now, if you want to run simulations manually, you need to carefully manipulate the flags in the define_simulation.v. See details about how in documentation: https://openfpga.readthedocs.io/en/master/manual/fpga_verilog/testbench/#cmdoption-arg-define_simulation.v

I believe this is a valid issue and we will soon update our testbench generator to avoid such confusion.