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lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
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A question about generating verilog code for FPGA #437

Closed kangliyu1 closed 2 years ago

kangliyu1 commented 2 years ago

Hello! I am very interested in this platform of OpenFPGA. Now I plan to use the K4N8 structure to generate a verilog of an EFPGA module with a size of 20*20 CLB on this platform. I would like to ask how I should do it? What parts need to be changed? I hope that some seniors can give some pointers, thank you very much!

tangxifan commented 2 years ago

You can refer to the syntax in VPR architecture file, which allows to change FPGA sizes. You can find details at VTR documentation

https://docs.verilogtorouting.org/en/latest/arch/reference/#fpga-grid-layout