The problem with pin constraints

[kangliyu1]

Hello! I recently used the k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml and k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml software of the OpenFPGA platform and generated a benchmark command with python3 openfpga_f_sw/task/CPU/DSPIO/FPGA/benchmark/macpy_fp/sw/task/Brain/FPGA/benchmark/mac_flow/sw/task. Produced the bitstream and other related documents of the benchmark circuit.

1. Are the pin constraints of the benchmark circuit defined by the .place file? How is the .place file in the folder generated after running the task of mac_units generated? How can I customize the pin constraints? Or how can I make the generated .place be the pin constraint I want to specify?
2. After running this task, the corresponding OpenFPGAshell.log file is generated, and some warnings appear in the file. As shown below, I am puzzled about these warnings and I don't know how to solve them. I hope someone can give me some advice. Very thanks! ! ! !

   ......
   # Loading Architecture Description
   Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
   Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
   Warning 3: Model 'frac_lut6' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
   Warning 4: Model 'frac_lut6' output port 'lut6_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
   Warning 5: Model 'frac_lut6' output port 'lut5_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
   Warning 6: Model 'frac_lut6' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
   ......
   Warning 7: Netlist contains 0 global net to non-global architecture pin connections
   ......
   ## Build tileable routing resource graph
   X-direction routing channel width is 300
   Y-direction routing channel width is 300
   Warning 8: in check_rr_node: RR node: 1998 type: OPIN location: (1,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 9: in check_rr_node: RR node: 2167 type: OPIN location: (3,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 10: in check_rr_node: RR node: 2258 type: OPIN location: (4,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 11: in check_rr_node: RR node: 2349 type: OPIN location: (5,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 12: in check_rr_node: RR node: 2728 type: OPIN location: (7,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 13: in check_rr_node: RR node: 2819 type: OPIN location: (8,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 14: in check_rr_node: RR node: 2910 type: OPIN location: (9,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 15: in check_rr_node: RR node: 3079 type: OPIN location: (11,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 16: in check_rr_node: RR node: 3170 type: OPIN location: (12,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 17: in check_rr_node: RR node: 3261 type: OPIN location: (13,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 18: in check_rr_node: RR node: 3640 type: OPIN location: (15,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 19: in check_rr_node: RR node: 3731 type: OPIN location: (16,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 20: in check_rr_node: RR node: 3822 type: OPIN location: (17,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   ........
   # Placement
   ## Computing placement delta delay look-up
   ### Build routing resource graph
   Warning 53: in check_rr_node: RR node: 3529 type: OPIN location: (1,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 54: in check_rr_node: RR node: 9309 type: OPIN location: (3,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 55: in check_rr_node: RR node: 13291 type: OPIN location: (4,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   Warning 56: in check_rr_node: RR node: 17273 type: OPIN location: (5,1) pin: 63 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
   .......
   Read OpenFPGA architecture
   Warning 144: Automatically set circuit model 'frac_lut6' to be default in its type.
   Warning 145: Automatically set circuit model 'MULTI_MODE_DFFSRQ' to be default in its type.
   Warning 146: Automatically set circuit model 'DFFR' to be default in its type.
   Warning 147: Automatically set circuit model 'GPIO' to be default in its type.
   ........
   Warning 149: Override the previous node '5088' by previous node '5089' for node '5060' with in routing context annotation!
   Warning 150: Override the previous node '5089' by previous node '5090' for node '5060' with in routing context annotation!
   Warning 151: Override the previous node '5090' by previous node '5111' for node '5060' with in routing context annotation!

   中文： 您好！我最近在使用OpenFPGA平台的k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml与k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml在使用python3 openfpga_flow/scripts/run_fpga_task.py benchmark_sweep/mac_units指令运行后，产生了一个带有DSP/BRAM/CLB/IO资源的FPGA软核，以及产生了benchmark电路的bitstream等相关文件。 1、请问关于benchmark电路的管脚约束是.place文件定义的吗？在运行完mac_units的task后产生的文件夹里的.place文件的怎么产生的？我该如何去自定义管脚约束呢？或者说我该如何使产生的.place是我想指定的管脚约束呢？ 2、在运行完这个task之后，产生了相应的OpenFPGAshell.log文件，在文件中出现了一些warning,如下所示,我对这些warning感到疑惑，不知道该怎么解决，希望有前辈可以指点一下。 非常感谢！！！！

[tangxifan]

For .place file, my method is

• Use VPR to do a placement without constraints and it will generate a .place file
• Modify the existing .place file by applying your pin constraints
• Rerun VPR where you skip packing and placement.