Closed kangliyu1 closed 2 years ago
@kangliyu1
-nolatches
option?synth -top Conv_2 -flatten
. @kangliyu1
- Can you try to remove the
-nolatches
option?- Can you tell which Yosys command causes the problem? According to the log file, my guess is the
synth -top Conv_2 -flatten
.- To identify if this is a bug from yosys or our tech lib, I suggest you to try other synthesis scripts through other test cases, e.g.,
- If other scripts/tech lib can pass, it is a problem of the yosys script.
- If other scripts have the same problem, it could be a problem of yosys. The bug should be reported to Yosys HQ: https://github.com/YosysHQ/yosys
Thank you very much for your reply! However, I still did not solve the problem yesterday. Regarding your reply to me on github, I will give you feedback
and so on......
@kangliyu1
@kangliyu1 Can you provide the openfpga version ? (You can see it by running OpenFPGA/openfpga/openfpga -v
@kangliyu1 Can you provide the openfpga version ? (You can see it by running
OpenFPGA/openfpga/openfpga -v
This is my openfpga version
@kangliyu1 We have improved many features in OpenFPGA since 2021-09-22, including Yosys upgrade. Can you give a try on the latest master?
We have improved many features in OpenFPGA since 2021-09-22, including Yosys upgrade. Can you give a try on the latest master?
Okay, thank you for your reply. I will try to use the upgraded version today. Does the upgraded openfpga still have functions? (For example, can PCf files be supported for pin constraints?) Also, vivado can generate edif files, and can the corresponding vpr be run in openfpga?
@kangliyu1 The major update is to bump Yosys version from 0.9 to latest 0.10 release Also we introduce new configuration protocols.
PCF and EDIF support is scheduled this year. It will be online.
Hello! I encountered a very strange problem. I synthesized a piece of code in yosys in openfpga (code is as follows code1). An error was reported during the synthesis process, as shown in Figure 1, but no error was pointed out in yosys_output.log Locally, alone, yosys found out that kill automatically exited in the corresponding place, so I am a little confused. I hope some seniors can give me some advice. Thank you very much! ! Note: The architecture uses k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml, k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml, iwls_benchmark_example_script.openfpga
fig1:![image](https://user-images.githubusercontent.com/76480905/148064797-69f83a87-1937-440e-80cb-c3401c62c6aa.png)
fig2:![image](https://user-images.githubusercontent.com/76480905/148064229-0c90d5ec-0da3-417a-b504-2441f3a5c3b1.png)
code1:
yosys scripts: