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lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
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I try to run openfpga shell which using yosys_vpr flow of the task flow, and find some error. #52

Closed colleen-rin closed 4 years ago

colleen-rin commented 4 years ago

Hi, I tried to run openfpga shell by using run_fpga_task.py. When the flow I chose was vpr_blif, the result was successful, but the flow I chose wasyosys_vpr, the result was error. This is report about the reason of the error.

00_FSM_top_MIN_ROUTE_CHAN_WIDTH_out.log

My solution was using yosys_vpr flow to runing the section of yosys first, then generating benchmark.blif, benchmark_ace_out.act, benchmark_output_verilog.v. Finally, using those three files to run vpr_blif flow. This can be a temporary way to run a complete flow of openfpga shell.

ganeshgore commented 4 years ago

yosys_vpr is still not completely supported with fpga_taskand OpenFPGA shell. In any case, can you share task.conf file

colleen-rin commented 4 years ago

Sure, this is task.conf and my benchmark zip file. task.conf.log FSM_three_code.zip