Sky130 Openfpga architecture

[ghost]

1 - Why Sky130 Openfpga architecture use 45nm.pm technology file as input. In this way are power and timing analysis results reliable? 2- `

10e-12 10e-12

` What this 10e-12 delay mean? If we want to generate a technology mapped Openfpga with another PDK, how can we determine this delay value? More spesificly, how much capacitance this inverter should be simulated with to determine this value?

[ganeshgore]

@msaideroglu In Sky130 architecture, we did not use VPR/OpenFPGA to measure the power and timing numbers. The power and timing analysis is performed directly on the Post PnR netlist.

[ghost]

Thanks @ganeshgore.