Some general questions about OpenFPGA

[ghost]

1-We have a tech-mapped netlist. When I synthesize a netlist from Design Compiler it generates its sdf file too. So that we can run realistic simulations on it. However now we have auto-mapped netlist already. How can we obtain its sdf file? Also there are sdc timing constraints generated. However those are adapted to PTM_40nm technology. For example there is a constrained as "set_max_delay -from fpga_top/cbx_1_0/chanx_left_in[0] -to fpga_top/cbx_1_0/chanx_left_out[0] 2.272500113e-12" in cbx_1_0.sdc. How and where can we define that delay value for our technology. I'm trying to map an architecture to our 250nm technology.

2- In SOFA and CLEAR fpgas k4n8 architecture is preferred. Why is it? Is there a better architecture which has higher performance like k6n10 etc.?

[tangxifan]

@mattvlsi

1. • If you have a tech mapped netlists, we suggest you to use SDC files when resynthesis on some circuits or blocks are required.
   • We are trying our best in OpenFPGA to generate the SDC files for you. When you see like

set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12

the delay number is extracted from the timing numbers defined in FPGA architecture. It is a step forward to our vision as described in https://openfpga.readthedocs.io/en/master/_images/fpga_sdc_motivation.png

• However, it is not so satisfying these days. We have realized this limitation and are actively searching for a solution. Please note that due to the large number of FPGA architectures supported by OpenFPGA, auto-generation of SDC files is a difficult problem. It may take us 1 year or 2 to develop.

• Therefore, currently, my suggestion to use OpenFPGA's SDC outputs as a reference and write your own SDC. In this way, you can find the best experience. If you see anything that should be updated in the SDC generator, feel free to contact us.

2. K4N8 is considered to a good choice for low-cost and low-power FPGAs. K6 series are in general considered as high-performance architectures. The conclusion is based on many architecture papers that have be published. See one at https://www.eecg.utoronto.ca/~jayar/pubs/ahmed/tvlsi_march_04.pdf

   However, these previous papers are based on FPGAs built with full custom layouts. As we are using a new methodology, the conclusion may be changed.

[ghost]

Thanks @tangxifan. When you say "the delay number is extracted from the timing numbers defined in FPGA architecture", did you mean this timing numbers in openfpga arch; ` 10e-12

10e-12 ` What exactly is this "**10e-12**" value? Is it rise/fall transition time or propagation delay high-to-low/low-to-high?

[tangxifan]

@mattvlsi

• The timing value on CBs are computed by using the arch timing parameters with a delay model of R*Cout + Tdel

https://github.com/lnis-uofu/OpenFPGA/blob/70e2330f1740786ac7a108fd4182d63ab75069d3/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml#L374

• The one you found is some cell-level propagation delay, which are used when --include_timing option is enabled when running the write_fabric_verilog command.

https://openfpga.readthedocs.io/en/master/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands/#cmdoption-include_timing

They are mainly used to help simulator converge.

[ghost]

Thanks @tangxifan