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lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
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Benchmarking a FIFO circuit #730

Open yunuseryilmaz18 opened 2 years ago

yunuseryilmaz18 commented 2 years ago

Describe the bug Hi. I've changed the benchmark circuit in fpga_verilog/bram/dpram1k task as FIFO circuit. However, Yosys creates black boxes which are not suitable for PnR in VPR, such as $alu and $_DFFEPP1P and this makes OpenFPGA flow crash.

Which part of OpenFPGA is buggy

  • [X] VPR

To Reproduce Steps to reproduce the behavior:

  1. Clone OpenFPGA repository and checkout commit id: 2e8d5aa65e36d3b185725848723d53c8ab9dbd4c
  2. Change the benchmark circuit of fpga_verilog/bram/dpram1k task as FIFO circuit.
  3. Run the task.
  4. See error.

Expected behavior I want to benchmark a FIFO circuit on a FPGA architecture with block RAM.

Screenshots Error logs: image VPR logs: image

Enviornment (please complete the following information):

  • OS:

    • [X] Ubuntu 20.04

  • Compiler:

    • [X] gcc-9
  • Version:
  • [X] Current master

Additional context Add any other context about the problem here.

tangxifan commented 2 years ago

@yunuseryilmaz18 I think this is more like a Yosys script issue. You see $alu and $DFFE_PP1P due to some mapping failures in Yosys.

Can you share which Yosys scripts you are using?

yunuseryilmaz18 commented 2 years ago

@tangxifan I'm using the template script in the repo.

msaideroglu commented 1 year ago

Hi @tangxifan. I'm facing same issue. How should I change Yosys script?