Full testbench freezes at the middle, but preconfigured testbench successfully completes

lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator

https://openfpga.readthedocs.io/en/master/

MIT License

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Full testbench freezes at the middle, but preconfigured testbench successfully completes #769

Closed msaideroglu closed 2 years ago

msaideroglu commented 2 years ago

Describe the bug I'm running testbenches with sky130 architecture files. When I synthesize a fabric and benchmarks for it, preconfigured testbenches are successfully runned. However when I run full_testbench for those benchmarks it freezes at the middle of configuration phase. I added FUNCTIONAL 1, and UNIT_DELAY #0.1 parameters to sky130_hd.v file. What could be the reason?

Version: Current master

tangxifan commented 2 years ago

@msaideroglu If you added the flags, it should help HDL simulators to converge easily. It should not slow down the simulation. Typically, simulators, e.g., modelsim, show debugging information / logs when they have problems in converging. Please checkout your log files.