Assertion "true == model_is_default(default_id)" is failed

[buddynohair]

Hello,

sorry for the disturb again. I kinda have a new problem. I made a few changes in the k6_frac_N10_adder_chain_40nm_openfpga.xml. For example, i wrote a 8-to-1 multiplexer and used it in the connection box. In addition i changed the configuration protocol with a new customized D-Flipflop. After i ran it manually, i got the response: Assertion "true == model_is_default(default_id)" is failed

Would you give me any advice?

[tangxifan]

Hello, Would you mind sharing your arch file?

[buddynohair]

Hello,

yes for sure

arch.zip task.log mux8to1.log d_ff.log

[tangxifan]

Hello, I think you forgot to set the default model for you FFs in your architecture file. We expect you to tell OpenFPGA in each type of circuit model, what is the default one, through syntax is_default OpenFPGA can automatically link pb_type or other FPGA resources to default models when not specified in your architecture file. Anyway, some check codes are required to tell users that a default model is necessary. I will patch this.

[buddynohair]

Ah ok thank you very much .

[buddynohair]

Hello,

can you please have a look on another issue ? I think the source code is generated but there's a problem with test bench generation.

k6_frac_N10_adder_chain_mem16K_40nm.zip

[tangxifan]

Hello, I checked your architecture file. You defined a new ccff circuit model called d_ff. The ccff is the flip-flop for programming circuitry. The clock signal of ccff should be a programming clock. However, you define it as a regular clock (XML syntax is_prog is set false). I do not know how you want to use the flip-flop. If it is part of programming circuitry, it should follow the ccff examples in your architecture file. If it is in the datapath, it should follow the ff examples in your architecture file. Currently, it mixed the two.

[buddynohair]

Hello,

i have solved this problem. thank you very much !