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lnis-uofu / OpenFPGA

An Open-source FPGA IP Generator
https://openfpga.readthedocs.io/en/master/
MIT License
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This circuit requires a channel width above 1000, probably is not going to route. #793

Closed zliu1Charlotte closed 2 years ago

zliu1Charlotte commented 2 years ago

i am doing a custom design but it failed on routing. I am using soft_adder example here are the files that i am using

openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml openfpga_vpr_circuit_format=eblif external_fabric_key_file=

Have you seen this error before?

(00_counterSBox_MIN_ROUTE_CHAN_WIDTH) - OpenFPGA Shell Run run failed with returncode 1 ERROR (00_counterSBox_MIN_ROUTE_CHAN_WIDTH) - command /home/pc-1/zliu/OpenFPGA/openfpga/openfpga -batch -f counterSBox_run.openfpga ERROR (00_counterSBox_MIN_ROUTE_CHAN_WIDTH) - -->>Error 1: ERROR (00_counterSBox_MIN_ROUTE_CHAN_WIDTH) - -->>Error 2: Command 'vpr' execution has fatal errors ERROR (00_counterSBox_MIN_ROUTE_CHAN_WIDTH) - Current working directory : /home/pc-1/zliu/OpenFPGA/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/run010/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm/counterSBox/MIN_ROUTE_CHAN_WIDTH ERROR (00_counterSBox_MIN_ROUTE_CHAN_WIDTH) - Failed to run OpenFPGA Shell Run task ERROR (00_counterSBox_MIN_ROUTE_CHAN_WIDTH) - Exiting . . . . . . ERROR (00_counterSBox_MIN_ROUTE_CHAN_WIDTH) - Failed to execute openfpga flow - 00_counterSBox_MIN_ROUTE_CHAN_WIDTH

here is the openfpgashell.log file:

Warning 209: No routing path for connection to sink_rr 1355, retrying with full device bounding box Cannot route from io_right.inpad[0] (RR node: 1836 type: SOURCE location: (5,4) class: 1 capacity: 1) to clb.clk[0] (RR node: type: SINK location: (4,3) class: 47 capacity: 1) -- no possible path Failed to route connection from 'clk' to 'DUT1.s[4]' for net 'clk' (#21) Routing failed.

Attempting to route at 1792 channels (binary search bounds: [896, -1]) Routing took 0.43 seconds (max_rss 24.2 MiB, delta_rss +7.7 MiB) The entire flow of VPR took 0.59 seconds (max_rss 24.2 MiB) Fatal error occurred! OpenFPGA Abort

Finish execution with 2 errors

The entire OpenFPGA flow took 0.588068 seconds

Thank you for using OpenFPGA! Error 1: Type: Routing File: /home/pc-1/zliu/OpenFPGA/vpr/src/base/place_and_route.cpp Line: 165 Message: This circuit requires a channel width above 1000, probably is not going to route. Aborting routing procedure. Error 2: Command 'vpr' execution has fatal errors 1

i tried with this but the same error is showing: [SCRIPT_PARAM_Fixed_Routing_1500] fix_route_chan_width=1500 end_flow_with_test= vpr_fpga_verilog_formal_verification_top_netlist=

msaideroglu commented 2 years ago

Hi @zliu1Charlotte . How did you solve this issue? I'm facing the same error.

zliu1Charlotte commented 2 years ago

this did not resolved, i went with other task.conf file sorry.