tangxifan
commented
1 year ago @lnyyyy In this embedded I/O, we just use FPGA_DIR to output the direction signal for SOC usage. In the example architecture file, the FPGA_DIR is controlled by a configuration bit and drive the FPGA_DIR port. You do not need to specify any configuration bits in vpr_arch file, as the information is covered by openfpga_arch only.
Hello, I try to use the EMBEDDED_IO_ISOLN defined in the gpio.v file in openfpga_cell_library to build an eFPGA. I found that the EMBEDDED_IO_ISOLN module does not use FPGA_DIR signal for direction control. Does this require the user to write the embedded_io module to implement the direction control function. `module EMBEDDED_IO_ISOLN ( input SOC_IN, // Input to drive the inpad signal output SOC_OUT, // Output the outpad signal output SOC_DIR, // Output the directionality output FPGA_IN, // Input data to FPGA input FPGA_OUT, // Output data from FPGA input FPGA_DIR, // direction control input IO_ISOL_N // Active-low signal to set the I/O in input mode );
assign FPGA_IN = IO_ISOL_N ? SOC_IN : 1'bz; assign SOC_OUT = IO_ISOL_N ? FPGA_OUT : 1'bz; // Direction signal is set to logic '0' when in input mode assign SOC_DIR = IO_ISOL_N ? FPGA_DIR : 1'b0; endmodule` And I checked an openfpga_arch file k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml, it shows support k4_frac_cc_sky130nm.xml structure, but I did not find this in the vpr_arch directory.