Closed abdullahyildiz closed 3 years ago
@abdullahyildiz You can find latest commit here: https://github.com/lnis-uofu/OpenFPGA/commit/ef3cbe708c9fd516500c09c22d97f1c6ee07d67d
When I try to run make runOpenFPGA
with the OpenFPGA release https://github.com/lnis-uofu/OpenFPGA/commit/ef3cbe708c9fd516500c09c22d97f1c6ee07d67d, I get write_full_testbench is not defined
error within openfpgashell.log:
@abdullahyildiz Sorry for the inconvenience. I merged the pull request https://github.com/lnis-uofu/SOFA/pull/123
Now you should be able to use the latest OpenFPGA on master branch.
@tangxifan,
No problem. Thanks also for your support.
This time I get the following error:
Write autocheck testbench for FPGA top-level Verilog netlist for 'counter'
Will use 78766 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'counter' took 0.00 seconds (max_rss 59.8 MiB, delta_rss +0.0 MiB)
Write Verilog full testbenches for FPGA fabric
took 0.00 seconds (max_rss 59.8 MiB, delta_rss +0.0 MiB)
Command line to execute: --reference_benchmark_file_path counter_output_verilog.v --explicit_port_mapping
Try to call a command '--reference_benchmark_file_path' which is not defined!
Fatal error occurred!
OpenFPGA Abort
Finish execution with 1 errors
The entire OpenFPGA flow took 1.46976 seconds
Thank you for using OpenFPGA!
1
Is something wrong with my setup?
@tangxifan,
I think the problem arises from a typo in L58 in generate_testbench.openfpga: https://github.com/lnis-uofu/SOFA/blob/45184c35ea578daecef76b26557b25fdbf6e8edd/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga#L58
There should be a backslash at the end of the line.
@abdullahyildiz Thanks for pointing this out. Should fix it asap
I get the following error when I try to run
make runOpenFPGA
with the latest OpenFPGA release:It seems that the command write_verilog_testbench is deprecated.
What is the latest compatible OpenFPGA commit id to be used within SOFA project?