Closed abdullahyildiz closed 3 years ago
I used the functional FF model instead of behavioral one to fix the problem:
> iverilog -o sim -DFUNCTIONAL -DUNIT_DELAY=#0 SRC/top_include_netlists.v -I$OPENLANE_ROOT/pdks/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv -I$OPENLANE_ROOT/pdks/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf -I$OPENLANE_ROOT/pdks/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2 -I$OPENLANE_ROOT/pdks/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2 -I$OPENLANE_ROOT/pdks/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp -I$OPENLANE_ROOT/pdks/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp -I$OPENLANE_ROOT/pdks/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b -I$OPENLANE_ROOT/pdks/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn
@abdullahyildiz You are right. We used the functional FF model in our verification. We fixed the same bug as you did. I encourage you to report the issue to the maintainers of the skywater open pdk. Just like we did before: https://github.com/google/skywater-pdk/issues/197
I did the following in order to run functional simulation of FPGA1212_SOFA_HD design with
and
benchmark in Icarus Verilog:However,
out_c_fpga
is displayed as 'X':I think the problem arises from using UDP instance in sky130_fd_sc_hd__dfxtp:
As shown, the signal
D_delayed
has the 'Z' value since it is not driven by any signal: