Closed ghost closed 2 years ago
Can you share the openfpgashell.log
file from the run directory
write_full_testbench
command is deprecated, please replace that command in your *.openfpga
file with following
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
Thanks. It is solved.
I'm getting this error during first test: "ERROR (00_counter_MIN_ROUTE_CHAN_WIDTH) - Failed to execute openfpga flow - 00_counter_MIN_ROUTE_CHAN_WIDTH . . .'python3 /home/msaid/OpenFPGA/openfpga_flow/scripts/run_fpga_flow.py ... _task/run001 /vpr_arch/counter /MIN_ROUTE_CHAN_WIDTH --vpr_fpga_x2p_rename_illegal_port' returned non-zero exit status 0. X X X X X X Failed to generate netlist X X X X X X " I have a running OpenFPGA installation.