Fix typos causing the unknown `write_verilog_testbench` command errors

lnis-uofu / SOFA

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

https://skywater-openfpga.readthedocs.io/en/latest/

MIT License

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Fix typos causing the unknown `write_verilog_testbench` command errors #134

Closed romangauchi closed 2 years ago

romangauchi commented 2 years ago

Hello, there is a small fix for:

found a missing backslash \ in various generate_tesbench.openfpga scripts, raising the unknown 'write_verilog_testbench' command error. I fix that typo for SOFA_HD, SOFA_CHD and SOFA_PLUS_HD task scripts,
adding a default task.conf in the config directory to ensure the execution of the 'run-task' command.

Thanks!

GrantBrown1994 commented 2 years ago

@romangauchi task.conf is not needed. The makefile is included to generate the task.conf from task_generation.conf. If users need specific changes to the task.conf they must clone and modify it locally on task_generation.conf.

romangauchi commented 2 years ago

@GrantBrown1994 I just remove the task.conf. Thanks!