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lnis-uofu / SOFA

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
https://skywater-openfpga.readthedocs.io/en/latest/
MIT License
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Unknown `write_verilog_testbench` command in the OpenFPGA flow #135

Closed romangauchi closed 2 years ago

romangauchi commented 2 years ago

Hello! While running the run-task command, with OpenFPGA framework for SOFA_CHD and SOFA_HD, I encountered an error from an unknown command: write_verilog_testbench. Please, find the details below.

Done with OpenFPGA revision df67a947 (2022-01-21), same behavior with the f72bf4b (2022-01-28)

End of openfpgashell.log error report for SOFA_CHD (full log attached here: SOFA_CHD_openfpgashell.log)

Command line to execute: write_verilog_testbench     --file ./SRC     --reference_benchmark_file_path top_output_verilog.v     --print_top_testbench     --print_preconfig_top_testbench     --print_simulation_ini ./SimulationDeck/simulation_deck.ini     --explicit_port_mapping
Try to call a command 'write_verilog_testbench' which is not defined!
Fatal error occurred!
OpenFPGA Abort

End of openfpgashell.log error report for SOFA_HD (full log attached here: SOFA_HD_openfpgashell.log)

Command line to execute: write_verilog_testbench     --file ./SRC     --reference_benchmark_file_path top_output_verilog.v     --print_top_testbench     --print_preconfig_top_testbench     --print_simulation_ini ./SimulationDeck/simulation_deck.ini     --explicit_port_mapping
Try to call a command 'write_verilog_testbench' which is not defined!
Fatal error occurred!
OpenFPGA Abort

Can you help me find out what could be the cause? Thanks!

romangauchi commented 2 years ago

Now fixed with the pull request #134