SOFA timing analysis with sdc file input does not give timing report

[ghost]

I'm doing counter benchmark on SOFA fpga. I gave a scd file input to do timing analysis. The sdc file definition of flow is written in generate_testbench.openfpga: vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off \ --sdc_file /home/msaid/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/BENCHMARK/counter_new/counter.sdc

My sdc file content is: create_clock -period 20 -name clk set_input_delay -clock clk -max 0 [get_ports {*}] set_output_delay -clock clk -max 0 [get_ports {*}]

However report_timing.setup.rpt does not show me anything. Its content is:

`#Timing report of worst 0 path(s)

End of timing report`

openfpgashell.log and vpr_stdout.log are attached: openfpgashell.log vpr_stdout.log