FPGA1212_QLSOFA_HD_task reproducing fabric netlists

[ghost]

I want to run generate_fabric task on QLSOFA_HD to be able to reproduce exactly same Verilog netlists with the one in repo. So I configured task.conf file same with task_generation.conf in QLSOFA_HD repo. Please look at my task.conf file below: task.txt However I'm getting this error in openfpgashell.log :

Error 1: ~/OpenFPGA/libs/libvtrutil/src/vtr_util.cpp:186 Failed to convert string '${OUTPAD_DELAY}' to float
Error 2: Command 'vpr' execution has fatal errors

I also runed make runOpenFPGA TASK_FILENAME=task_generation.conf in QLSOFAHD repo. It executed, but there was no Verilog netlist files in **/SRC_** directory. How can I reproduce Verilog netlists?

Thanks.

@ganeshgore

[ganeshgore]

Seems link you are not linking the design variable file. There is a ${OUTPAD_DELAY} in the architecture file which is not resolved.

This is where we define the design variable file
https://github.com/lnis-uofu/SOFA/blob/e508bdd9056639101993f84a215ab10354659ad6/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_generation.conf#L16

The variable is defined here https://github.com/lnis-uofu/SOFA/blob/e508bdd9056639101993f84a215ab10354659ad6/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/design_variables.yml#L12

[ghost]

Thanks a a lot for your return @ganeshgore. Now that error is gone. Still getting something little. openfpgashell.txt

[ganeshgore]

Some file path is missing.

[ghost]

Thanks @ganeshgore. I successfully obtain fabric netlists now. I'm running generate_tetbench.openfpga with task_simulation.conf in task directory. Should I expect to see iverilog.txt and and2_formal.vcd files in task directory just like in generate_testbench tasks in OpenFPGA? Because it isn't generated. Or how can I do the iverilog simulations by manually?