Closed msaideroglu closed 1 year ago
those are routing delays which are calculated based on RC value provided in the design_variable.yml file https://github.com/lnis-uofu/SOFA/blob/e508bdd9056639101993f84a215ab10354659ad6/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/design_variables.yml#L5-L10
These delays are dynamically calculated based on the routing wire length, hence you dont find exact number.
Understood. Thanks.
I am looking at SOFA_HD task. design_variables.yml includes delay parameters of primitives. When I run a benchmark on SOFA_HD, for instance a counter benchmark the setup timing report says:
I can understand 0.11, 0.43, 1.14 and 0.86 ns etc. values comes directly from design variables. But I couldn't realize where those 10.32, 10.89, 4.45 ns values come from?