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lnis-uofu / SOFA

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
https://skywater-openfpga.readthedocs.io/en/latest/
MIT License
128 stars 25 forks source link

Cannot run with newest version of OpenFPGA #147

Closed franktaTian closed 4 months ago

franktaTian commented 4 months ago

I use ther docker of OpenFPGA( according the Document) And clone the SOFA (this site) docker run -it -v ./SOFA:/home/openfpga_user/SOFA ghcr.io/lnis-uofu/openfpga-master Then , try to run SOFA , there is error :

openfpga_user@8ca4305f0016:\~/SOFA/FPGA1212_QLSOFA_HD_PNR$ make runOpenFPGA OPENFPGA_PATH=/opt/openfpga shopt INFO ( MainThread) - Set up to run 2 Parallel threads INFO ( MainThread) - Currently running task FPGA1212_QLSOFA_HD_task INFO ( MainThread) - Removing run_dir run001 INFO ( MainThread) - Removing run_dir latest INFO ( MainThread) - Task execution completed INFO ( MainThread) - Set up to run 2 Parallel threads INFO ( MainThread) - Currently running task FPGA1212_QLSOFA_HD_task INFO ( MainThread) - Created "run001" directory for current task run INFO ( MainThread) - Running "yosys_vpr" flow INFO ( MainThread) - Found 1 Architectures 1 Benchmarks & 1 Script Parameters INFO ( MainThread) - Created total 1 jobs ERROR (00_counter_MIN_ROUTE_CHAN_WIDTH) - Failed to execute openfpga flow - 00_counter_MIN_ROUTE_CHAN_WIDTH Traceback (most recent call last): File "/opt/openfpga/openfpga_flow/scripts/run_fpga_task.py", line 572, in run_single_script raise subprocess.CalledProcessError(0, " ".join(command)) subprocess.CalledProcessError: Command 'python3.8 /opt/openfpga/openfpga_flow/scripts/run_fpga_flow.py /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/BENCHMARK/counter/counter.v --top_module counter --run_dir /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH --fpga_flow yosys_vpr --openfpga_shell_template /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga --openfpga_arch_file /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml --openfpga_sim_setting_file /opt/openfpga/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml --external_fabric_key_file /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml --openfpga_vpr_device_layout 12x12 --openfpga_vpr_route_chan_width 60 --power --power_tech /opt/openfpga/openfpga_flow/tech/PTM_45nm/45nm.xml --arch_variable_file /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/design_variables.yml --vpr_fpga_verilog --vpr_fpga_verilog_dir /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH --vpr_fpga_x2p_rename_illegal_port --flow_config /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task.conf --default_tool_path /opt/openfpga/openfpga_flow/scripts/../misc/fpgaflow_default_tool_path.conf --TOP counter' returned non-zero exit status 0. X X X X X X Failed to generate netlist X X X X X X AND try to rerun the command: openfpga_user@8ca4305f0016:\~/SOFA/FPGA1212_QLSOFA_HD_PNR$ python3.8 /opt/openfpga/openfpga_flow/scripts/run_fpga_flow.py /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/BENCHMARK/counter/counter.v --top_module counter --run_dir /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH --fpga_flow yosys_vpr --openfpga_shell_template /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga --openfpga_arch_file /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml --openfpga_sim_setting_file /opt/openfpga/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml --external_fabric_key_file /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml --openfpga_vpr_device_layout 12x12 --openfpga_vpr_route_chan_width 60 --power --power_tech /opt/openfpga/openfpga_flow/tech/PTM_45nm/45nm.xml --arch_variable_file /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/design_variables.yml --vpr_fpga_verilog --vpr_fpga_verilog_dir /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH --vpr_fpga_x2p_rename_illegal_port --flow_config /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task.conf --default_tool_path /opt/openfpga/openfpga_flow/scripts/../misc/fpgaflow_default_tool_path.conf --TOP counter INFO - Validating command line arguments INFO - Run directory : /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH INFO - Running "yosys_vpr" Flow INFO - Extracted lut_size size from arch XML = 4 INFO - Running Yosys with lut_size = 4 INFO - Launching Run yosys INFO - Run yosys is written in file yosys_output.log INFO - ACE2 output is written in file counter_ace2_output.txt INFO - blif_3args output is written in file counter_blif_3args_output.txt INFO - Launching Yosys INFO - Yosys is written in file yosys_rewrite.log INFO - Running OpenFPGA Shell Engine INFO - Launching OpenFPGA Shell Run INFO - OpenFPGAShell Revision: v8.0.0-9402-geb9722851 Compiled: 2024-04-14T00:12:57 ERROR - OpenFPGA Shell Run run failed with returncode -6 ERROR - command /opt/openfpga/build/openfpga/openfpga -batch -f counter_run.openfpga ERROR - -->>terminate called after throwing an instance of 'ArchFpgaError' ERROR - -->> what(): Unexpected tag in section , expected ERROR - Current working directory : /home/openfpga_user/SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/counter/MIN_ROUTE_CHAN_WIDTH ERROR - Failed to run OpenFPGA Shell Run task ERROR - Exiting . . . . . .

franktaTian commented 4 months ago

Any help?

Lukemagik commented 4 months ago

Hi @franktaTian did you solve the problem ?

franktaTian commented 4 months ago

Hi @franktaTian did you solve the problem ?

Not yet. I think there maybe some mismatch of version. It is hard for me to debug it.

Lukemagik commented 4 months ago

Hi @franktaTian If it can be helpful, I solved it by replacing in generate_generate_testbench.openfpga file: '--load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}' with 'generate_random_key'.

image

franktaTian commented 4 months ago

Hi @franktaTian If it can be helpful, I solved it by replacing in generate_generate_testbench.openfpga file: '--load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}' with 'generate_random_key'.

image

Thank you for your help. I will try it.

franktaTian commented 4 months ago

Yes,It can work now!