VCXO 20 MHz (BOOT_CLK_IN) is connected to incompatible FPGA bank

lnls-dig / afc-hw

AMC FMC Carrier electronic and mechanical projects

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VCXO 20 MHz (BOOT_CLK_IN) is connected to incompatible FPGA bank #25

Open lerwys opened 7 years ago

lerwys commented 7 years ago

Problem: VCXO026156 (20 MHz VCXO) is connected to both the clock switch ADN4604ASVZ and to FPGA Bank 33 BOOT_CLK_IN.

However, back 33 is the DDR bank, which must used the SSTL15 I/O standard and BOOT_CLK_IN is a LVCMOS25.

aylons commented 4 years ago

Hi, @lerwys ! What is the severity of this bug? Is something not working properly or is a potential issue? Changing FPGA pins in this board is a musical chairs game...