aylons
commented
8 years ago The problem is the ADN4604 input for the bidirectional clock, which has termination resistors which increases the differential load of the LVDS line from the 100 ohms to about 50 ohms. The result is a lower LVDS voltage, as the LVDS has constant current.
For now, a workaround is to remove capacitors:
C491, C493 for FMC1_CLK2_BIDIR C495, C497 for FMC1_CLK3_BIDIR C507, C509 for FMC2_CLK2_BIDIR C511, C513 for FMC2_CLK3_BIDIR
The ADN4604 allows disabling the receiver resistors, however, this can only be done for a full quadrant, which are half the inputs (either 01-07 or 08-15). We can either regroup the clocks, so this is less of an issue, or we can buffer the bidirectional clocks so the FMC output is not affect by the ADN termination.
During some tests we tried to route a clock signal from the clock switch (ADN4604) to the FMC boards using the FIN1101 'buffers'. We discovered that the voltage swing from the FIN1101 output is not large enough to be detected by the FMC ADC, so we couldn't lock the ADC PLL with our reference clock. In order to solve this, we bypassed all the FIN1101 using small wires, routing the signal directly from the ADN4604 to the PLL on the FMC.
Note that the ADN4604 outputs that are connected on the FIN1101 don't have coupling capacitors like the rest of the switching matrix, we haven't tested if a series capacitor in this clock line would have any effects.