Closed lerwys closed 7 years ago
This is done in lnls-dig/infra-cores@1bda7f6aa3291223c461acaa9ce109d6aceebfa7 and lnls-dig/infra-cores@3dba4da48140b97a17d481153f277d36a018ca07.
In the software part, this is done by commit b2fa2fc02faefe819ba4367cb202649c01cf2e69
Problem: Currently, we rely on the END_CHAN_ID macro to iterate through the number of FPGA channels. This information should be read from FPGA as descriptor, not hardcoded in the software.
Solution: Add register describing the number of channels in the acq module;