[CLOSED] [smio:fmc130m_4ch] Fix off-by-one ADC channel 1

lnls-dig / halcs

Hardware Abstraction Layer for Control Systems

GNU General Public License v3.0

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Closed lerwys closed 8 years ago

lerwys commented 8 years ago

Issue by lerwys Thursday Oct 16, 2014 at 14:38 GMT Originally opened as https://github.com/lnls-dig/bpm-sw/issues/38

Problem: The ADC channel 1 is delayed by one clock cycle.

Possible Solution: Adjust the ADC delays.

lerwys commented 8 years ago

Comment by lerwys Saturday Jan 30, 2016 at 13:18 GMT

Could not reproduce. Probably an FPGA gateware which was fixed in the meantime