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lnls-dig / halcs

Hardware Abstraction Layer for Control Systems
GNU General Public License v3.0
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[CLOSED] [smio:acq] Can't read DDR3 past 0x0FFFFFFF #39

Closed lerwys closed 8 years ago

lerwys commented 8 years ago

Issue by lerwys Monday Oct 20, 2014 at 17:50 GMT Originally opened as https://github.com/lnls-dig/bpm-sw/issues/39

Problem: On acquisition we can't perform reads from DDR3 past address 0x0FFFFFFF. Maybe this is related to the BAR2 page switching or the FPGA BAR2 paging addressing.

lerwys commented 8 years ago

Comment by lerwys Monday Nov 03, 2014 at 11:06 GMT

Maybe this is a problem with the FPGA firmware, in which the DDR3 memory address is wrong?

lerwys commented 8 years ago

Comment by lerwys Tuesday May 12, 2015 at 20:33 GMT

Doesn't seem resolved. The read data is always the same, as if the acqusiition module is writing data to a different address as the one we are reading from.