lnls-dig / sinap-timing-epics-ioc

EPICS IOC support for SINAP Timing modules developed to compose the Sirius Timing System.
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Review CALC records + Optimize EVRE FPGA clock #46

Open mmdonatti opened 4 months ago

mmdonatti commented 4 months ago

Main goals

Changed/Created/Deleted Records

EVG

EVR

EVE

FOUT

See #45 to track history!

mmdonatti commented 4 months ago

WARNING: current implementation breaks EVG init sequencer sncEVGSetup.stt. Solved!