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lofaldli / gr-ccsds

GNU Radio module for Reed Solomon coded CCSDS frames
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implement support for the CCSDS standard for TC sync. and channel coding also #6

Open lofaldli opened 6 years ago

lofaldli commented 6 years ago

for now, only CCSDS 131 is supported, CCSDS 231 defines the TC standard

warmonkey commented 5 years ago

https://github.com/opensatellite/KS-1Q in this repo there is a working ccsds radio for satellite and another design for ground station. https://github.com/opensatellite/KS-1Q/blob/master/host/gr-kcsa-ks1q/lib/ccsds_tc_impl.cc here implemented CCSDS 231 telecommand BCH(63, 56) encoding.

warmonkey commented 5 years ago

BCH(63, 56) decoding we were built on fpga, and there's no c code. in file https://github.com/opensatellite/KS-1Q/blob/master/firmware/TTC_V04_FPGA/hdl/CLTU.v we didn't use chien search to find error bit, since BCH(63, 56) is 1-bit correction, we can use an Look-up table. first we shift in data bits (56) to an LFSR

`Syn_reg[0]<=Syn_reg[6]^DataI;          //BCH(63,56) calculate the syndromes
                            Syn_reg[1]<=Syn_reg[0];
                            Syn_reg[2]<=Syn_reg[1]^Syn_reg[6]^DataI;
                            Syn_reg[3]<=Syn_reg[2];
                            Syn_reg[4]<=Syn_reg[3];
                            Syn_reg[5]<=Syn_reg[4];
                            Syn_reg[6]<=Syn_reg[5]^Syn_reg[6]^DataI;`

then compare parity(7bits) with LFSR content (Syn_reg), if not equal, get error position using table below.

if((Syn_reg^Parity^7'b111_1111)!=0) begin  //1 bit error detection and correction
//if( 0) begin
                            case(Syn_reg^Parity^7'b111_1111)        //error detection and correction and jump to State2_S1(send data)
                                98:  begin Shift_reg[55]<=Shift_reg[55]+1; State2<=State2_S1; end   
                                49:  begin Shift_reg[54]<=Shift_reg[54]+1; State2<=State2_S1; end
                                122: begin Shift_reg[53]<=Shift_reg[53]+1; State2<=State2_S1; end
                                61:  begin Shift_reg[52]<=Shift_reg[52]+1; State2<=State2_S1; end
                                124: begin Shift_reg[51]<=Shift_reg[51]+1; State2<=State2_S1; end
                                62:  begin Shift_reg[50]<=Shift_reg[50]+1; State2<=State2_S1; end
                                31:  begin Shift_reg[49]<=Shift_reg[49]+1; State2<=State2_S1; end
                                109: begin Shift_reg[48]<=Shift_reg[48]+1; State2<=State2_S1; end
                                84:  begin Shift_reg[47]<=Shift_reg[47]+1; State2<=State2_S1; end
                                42:  begin Shift_reg[46]<=Shift_reg[46]+1; State2<=State2_S1; end
                                21:  begin Shift_reg[45]<=Shift_reg[45]+1; State2<=State2_S1; end
                                104: begin Shift_reg[44]<=Shift_reg[44]+1; State2<=State2_S1; end
                                52:  begin Shift_reg[43]<=Shift_reg[43]+1; State2<=State2_S1; end
                                26:  begin Shift_reg[42]<=Shift_reg[42]+1; State2<=State2_S1; end
                                13:  begin Shift_reg[41]<=Shift_reg[41]+1; State2<=State2_S1; end
                                100: begin Shift_reg[40]<=Shift_reg[40]+1; State2<=State2_S1; end
                                50:  begin Shift_reg[39]<=Shift_reg[39]+1; State2<=State2_S1; end
                                25:  begin Shift_reg[38]<=Shift_reg[38]+1; State2<=State2_S1; end
                                110: begin Shift_reg[37]<=Shift_reg[37]+1; State2<=State2_S1; end
                                55:  begin Shift_reg[36]<=Shift_reg[36]+1; State2<=State2_S1; end
                                121: begin Shift_reg[35]<=Shift_reg[35]+1; State2<=State2_S1; end
                                94:  begin Shift_reg[34]<=Shift_reg[34]+1; State2<=State2_S1; end
                                47:  begin Shift_reg[33]<=Shift_reg[33]+1; State2<=State2_S1; end
                                117: begin Shift_reg[32]<=Shift_reg[32]+1; State2<=State2_S1; end
                                88:  begin Shift_reg[31]<=Shift_reg[31]+1; State2<=State2_S1; end
                                44:  begin Shift_reg[30]<=Shift_reg[30]+1; State2<=State2_S1; end
                                22:  begin Shift_reg[29]<=Shift_reg[29]+1; State2<=State2_S1; end
                                11:  begin Shift_reg[28]<=Shift_reg[28]+1; State2<=State2_S1; end
                                103: begin Shift_reg[27]<=Shift_reg[27]+1; State2<=State2_S1; end
                                81:  begin Shift_reg[26]<=Shift_reg[26]+1; State2<=State2_S1; end
                                74:  begin Shift_reg[25]<=Shift_reg[25]+1; State2<=State2_S1; end
                                37:  begin Shift_reg[24]<=Shift_reg[24]+1; State2<=State2_S1; end
                                112: begin Shift_reg[23]<=Shift_reg[23]+1; State2<=State2_S1; end
                                56:  begin Shift_reg[22]<=Shift_reg[22]+1; State2<=State2_S1; end
                                28:  begin Shift_reg[21]<=Shift_reg[21]+1; State2<=State2_S1; end
                                14:  begin Shift_reg[20]<=Shift_reg[20]+1; State2<=State2_S1; end
                                7:   begin Shift_reg[19]<=Shift_reg[19]+1; State2<=State2_S1; end
                                97:  begin Shift_reg[18]<=Shift_reg[18]+1; State2<=State2_S1; end
                                82:  begin Shift_reg[17]<=Shift_reg[17]+1; State2<=State2_S1; end
                                41:  begin Shift_reg[16]<=Shift_reg[16]+1; State2<=State2_S1; end
                                118: begin Shift_reg[15]<=Shift_reg[15]+1; State2<=State2_S1; end
                                59:  begin Shift_reg[14]<=Shift_reg[14]+1; State2<=State2_S1; end
                                127: begin Shift_reg[13]<=Shift_reg[13]+1; State2<=State2_S1; end
                                93:  begin Shift_reg[12]<=Shift_reg[12]+1; State2<=State2_S1; end
                                76:  begin Shift_reg[11]<=Shift_reg[11]+1; State2<=State2_S1; end
                                38:  begin Shift_reg[10]<=Shift_reg[10]+1; State2<=State2_S1; end
                                19:  begin Shift_reg[9]<=Shift_reg[9]+1; State2<=State2_S1; end
                                107: begin Shift_reg[8]<=Shift_reg[8]+1; State2<=State2_S1; end
                                87:  begin Shift_reg[7]<=Shift_reg[7]+1; State2<=State2_S1; end
                                73:  begin Shift_reg[6]<=Shift_reg[6]+1; State2<=State2_S1; end
                                70:  begin Shift_reg[5]<=Shift_reg[5]+1; State2<=State2_S1; end
                                35:  begin Shift_reg[4]<=Shift_reg[4]+1; State2<=State2_S1; end
                                115: begin Shift_reg[3]<=Shift_reg[3]+1; State2<=State2_S1; end
                                91:  begin Shift_reg[2]<=Shift_reg[2]+1; State2<=State2_S1; end
                                79:  begin Shift_reg[1]<=Shift_reg[1]+1; State2<=State2_S1; end
                                69:  begin Shift_reg[0]<=Shift_reg[0]+1; State2<=State2_S1; end
                                64:  begin Parity[6]<=Parity[6]+1; State2<=State2_S1; end
                                32:  begin Parity[5]<=Parity[5]+1; State2<=State2_S1; end
                                16:  begin Parity[4]<=Parity[4]+1; State2<=State2_S1; end
                                8:   begin Parity[3]<=Parity[3]+1; State2<=State2_S1; end
                                4:   begin Parity[2]<=Parity[2]+1; State2<=State2_S1; end
                                2:   begin Parity[1]<=Parity[1]+1; State2<=State2_S1; end
                                1:   begin Parity[0]<=Parity[0]+1; State2<=State2_S1; end
                                default:begin   //cannot find the error bit, discard the block

if i have time i will finish c code

warmonkey commented 5 years ago

CCSDS 231 new standard added LDPC(128,64) and LDPC(512,256) for better uplink performance. that's insane. these short codes can be easily encoded on pc, achieve several hundreds Mbps. or use bp algorithm to decode, which is rather slow ( ~1Mbps for length 512 code )