Create features list of initial version

[louieb117]

A list of the basic features of the simplest initial version

[louieb117]

The initial design will have the following features

• Parse ARP network packets
• Save parsed data into primary memory
• Move parse data the secondary memory
• MIPS processor will reach the parsed data for matching IP address
• With FPGA control IO, switch modes from searching for in bound IPv4 address, out bound IPv4 address, or in bound MAC address
• ARP Field Addressable Memory

[louieb117]

Below is a high level features list that breaks down what is expected out of the baseline of the project.

• Feature a Basys3

• Process ARP IPv4 packets with dedicated digit hardware

  • Parse ARP network packets
  • Save parsed data into primary memory
  • Move parse data the secondary memory

• Feature a MIPS 32 bit Single Cycle Processor

• Feature external SRAM and EEPROM

• MIPS processor will pull the parsed data for matching IP address

• With FPGA control IO, switch modes from searching for in bound IPv4 address, out bound IPv4 address, or in bound MAC address

• ARP Field Addressable Memory