The proposed project this semester was to implement a simple network processor on the Basys3 platform with a primare functionality to parse ARP Packets into an ARP Field Addressable Memory.The key components that make up this project will be a single-cycle MIPS 32-bit processor and an APR Packet Processor.
The single-cycle processor design will closely follow the design outlined in Dr. Alimohammad's book COMPE 475 - Microprocessors. The APR Packet Processor will handle packet disassembly, data parsing, and storage in an ARP Field Addressable Memory. An additional stretch goal feature would implement a DMAC that will allow efficient handling of incoming TCP traffic by directing it to memory for access by other processors.
In parallel, I will conduct a thorough analysis and documentation of the specifications pertaining to interactions with NOR Flash memory and SRAM memory units.
Below is a high level features list that breaks down what is expected out of the baseline of the project.
Feature a Basys3
Process ARP IPv4 packets with dedicated digit hardware
Parse ARP network packets
Save parsed data into primary memory
Move parse data the secondary memory
Feature a MIPS 32 bit Single Cycle Processor
Feature external SRAM and EEPROM
MIPS processor will pull the parsed data for matching IP address
With FPGA control IO, switch modes from searching for in bound IPv4 address, outbound IPv4 address, or in bound MAC address
ARP Field Addressable Memory
The proposed project this semester was to implement a simple network processor on the Basys3 platform with a primare functionality to parse ARP Packets into an ARP Field Addressable Memory.The key components that make up this project will be a single-cycle MIPS 32-bit processor and an APR Packet Processor.
The single-cycle processor design will closely follow the design outlined in Dr. Alimohammad's book COMPE 475 - Microprocessors. The APR Packet Processor will handle packet disassembly, data parsing, and storage in an ARP Field Addressable Memory. An additional stretch goal feature would implement a DMAC that will allow efficient handling of incoming TCP traffic by directing it to memory for access by other processors.
In parallel, I will conduct a thorough analysis and documentation of the specifications pertaining to interactions with NOR Flash memory and SRAM memory units.
Below is a high level features list that breaks down what is expected out of the baseline of the project. Feature a Basys3 Process ARP IPv4 packets with dedicated digit hardware Parse ARP network packets Save parsed data into primary memory Move parse data the secondary memory Feature a MIPS 32 bit Single Cycle Processor Feature external SRAM and EEPROM MIPS processor will pull the parsed data for matching IP address With FPGA control IO, switch modes from searching for in bound IPv4 address, outbound IPv4 address, or in bound MAC address ARP Field Addressable Memory