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lowRISC / ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
https://www.lowrisc.org
Apache License 2.0
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Yosys syn flow: Use fusesoc #1006

Open imphil opened 4 years ago

imphil commented 4 years ago

The Yosys flow in syn currently ingests source files from the rtl directory and other places, feeds them through sv2v, and then passes them through yosys.

Since https://github.com/lowRISC/ibex/pull/994 we have a nicer way of calling sv2v through fusesoc; and a yosys-without-sv2v flow might not be too far away either.

Depending on how things evolve, we have two options to use fusesoc for the syn flow, and make use of its ability to generate target-dependent primitives, like the clock gating ones.

imphil commented 4 years ago

Related to #501 for the clock gating primitive.

towoe commented 4 years ago

and a yosys-without-sv2v flow might not be too far away either.

@imphil do you mean by that a sufficient SystemVerilog support by yosys?

imphil commented 4 years ago

Yes. Antmicro is using Ibex as test bed for Yosys improvements, and all necessary patches are available in https://github.com/antmicro/ibex-yosys-build. These patches are now making slowly their way upstream.

imphil commented 4 years ago

See https://github.com/lowRISC/ibex/issues/60 for details of the remaining issues we know about.