search

lowRISC / ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
https://www.lowrisc.org
Apache License 2.0
1.34k stars 523 forks source link

Cannot find assembly test #1071

Closed aliess closed 3 years ago

aliess commented 4 years ago

When I am trying to run UVM tests, using the below command to generate riscv_jump_stress_test for example:

make SIMULATOR=questa TEST=riscv_jump_stress_test ISS=spike ISA=rv32imc

will result in the below error log: 

Wed, 12 Aug 2020 18:33:46 INFO     Creating output directory: out/seed-25749/instr_gen
Wed, 12 Aug 2020 18:33:46 INFO     Processing regression test list : riscv_dv_extension/testlist.yaml, test: riscv_jump_stress_test
Wed, 12 Aug 2020 18:33:46 INFO     Found matched tests: riscv_jump_stress_test, iterations:1
Wed, 12 Aug 2020 18:33:46 INFO     Processing simulator setup file : /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/simulator.yaml
Wed, 12 Aug 2020 18:33:46 INFO     Found matching simulator: questa
Wed, 12 Aug 2020 18:33:46 INFO     Building RISC-V instruction generator
Wed, 12 Aug 2020 18:33:51 INFO     Running RISC-V instruction generator
Wed, 12 Aug 2020 18:33:51 INFO     Generating 1 riscv_jump_stress_test
Wed, 12 Aug 2020 18:33:51 INFO     Running riscv_jump_stress_test with 1 batches
Wed, 12 Aug 2020 18:33:51 INFO     Running riscv_jump_stress_test, batch 1/1, test_cnt:1
Wed, 12 Aug 2020 18:33:57 INFO     Creating output directory: out/seed-25749/instr_gen
Wed, 12 Aug 2020 18:33:57 INFO     Processing regression test list : riscv_dv_extension/testlist.yaml, test: riscv_jump_stress_test
Wed, 12 Aug 2020 18:33:57 INFO     Found matched tests: riscv_jump_stress_test, iterations:1
Wed, 12 Aug 2020 18:33:57 ERROR    Cannot find assembly test: out/seed-25749/instr_gen/asm_tests/riscv_jump_stress_test_0.S

make: *** [Makefile:273: out/seed-25749/.metadata/instr_gen.compile.stamp] Error 1

The assembly file in indeed not generated and not found in the out directory, and I can't seem to find any error python is throwing in order to debug the issue.

This doesn't happen when testing riscv_arithmetic_basic_test using the below command:

make SIMULATOR=questa TEST=riscv_arithmetic_basic_test ISS=spike ISA=rv32imc

This would run normally and finish successfully, however every other test other than the riscv_arithmetic_basic_test will fail as above.

rswarbrick commented 4 years ago

This is a little tricky to debug because the Makefile doesn't spit out commands as it goes (not my preferred style!). Can you run an example again with something like this?

make --trace SIMULATOR=questa TEST=riscv_jump_stress_test ISS=spike ISA=rv32imc SEED=1 ITERATIONS=1

That should show exactly which command is failing.

Also, could you look in your build directory? I end up with out/seed-1/instr_gen/asm_tests/riscv_jump_stress_test_0.S: I assume that file is missing? If so, it looks like something isn't running correctly with the instruction generator. You can run that on its own with the gen target (add "gen" to the end of the command line above). As a sanity check, can you search for .S files in the build tree with something like find -name '*.S' out/seed-1?

rswarbrick commented 4 years ago

As a note: We use VCS, rather than Questa, at lowRISC. It looks like there should be support for Questa, but it's possible that something has broken with that without us noticing. If so, thanks for the bug report(!) but we might have to do a bit of back-and-forth to work out what's not working.

aliess commented 4 years ago

using the command you provided:

make --trace SIMULATOR=questa TEST=riscv_jump_stress_test ISS=spike ISA=rv32imc SEED=1 ITERATIONS=1

produces the below log: 

Makefile:125: target 'out' does not exist
mkdir -p out
Makefile:142: update target 'out/.sim-cfg.mk' due to: FORCE
./sim_makefrag_gen.py questa experimental-maxperf-pmp-bmfull /home/ali/Documents/ibex out/.sim-cfg.mk
Makefile:125: target 'out/seed-1/.metadata' does not exist
mkdir -p out/seed-1/.metadata
Makefile:247: update target 'out/seed-1/.metadata/instr_gen.gen.stamp' due to: FORCE /home/ali/Documents/ibex/vendor/google_riscv-dv/README.md /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_base_test.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_cov_test.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_test.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_gen_tb_top.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_test_pkg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/setup.cfg /home/ali/Documents/ibex/vendor/google_riscv-dv/design.bin /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/link.ld /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/ovpsim_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/sail_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/deprecated/ovpsim_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/deprecated/spike_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/deprecated/riscv_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/deprecated/instr_trace_compare.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/gen_csr_test.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/ovpsim_log_to_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/riscv_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/instr_trace_compare.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/whisper_log_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/sail_log_to_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/spike_log_to_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/lib.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/riscv_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/whisper_log_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/instr_trace_compare.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/lib.py /home/ali/Documents/ibex/vendor/google_riscv-dv/run.py /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gcv/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gcv/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gcv/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32i/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32i/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32i/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/multi_harts/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/multi_harts/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/multi_harts/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imcb/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imcb/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imcb/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gc/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gc/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gc/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imc/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imc/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imc/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imc/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imc/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imc/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imcb/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imcb/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imcb/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/ml/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/ml/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/ml/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/MANIFEST.in /home/ali/Documents/ibex/vendor/google_riscv-dv/cov.py /home/ali/Documents/ibex/vendor/google_riscv-dv/.flake8 /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_asm_program_gen.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/test/out/.gitkeep /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/test/riscv_instr_base_test.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_defines.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_instr_gen_config.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_instr_sequence.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/target/rv32i/riscv_core_setting.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_instr_pkg.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/isa/rv32i_instr.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_instr.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_instr_stream.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/README.md /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_asm_program_gen.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/utils.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_instr_sequence.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_callstack_gen.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_rand_instr.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_directed_instr_lib.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_load_store_instr_lib.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_instr_stream.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_data_page_gen.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_instr_base.py /home/ali/Documents/ibex/vendor/google_riscv-dv/.gitignore /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/cov_testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/csr_template.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/iss.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/simulator.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/base_testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/LICENSE.txt /home/ali/Documents/ibex/vendor/google_riscv-dv/.travis.yml /home/ali/Documents/ibex/vendor/google_riscv-dv/questa_sim.tcl /home/ali/Documents/ibex/vendor/google_riscv-dv/qrun_option.f /home/ali/Documents/ibex/vendor/google_riscv-dv/CONTRIBUTING.md /home/ali/Documents/ibex/vendor/google_riscv-dv/riscv.ucdb /home/ali/Documents/ibex/vendor/google_riscv-dv/setup.py /home/ali/Documents/ibex/vendor/google_riscv-dv/vcs.compile.option.f /home/ali/Documents/ibex/vendor/google_riscv-dv/riviera_sim.tcl /home/ali/Documents/ibex/vendor/google_riscv-dv/user_extension/user_extension.svh /home/ali/Documents/ibex/vendor/google_riscv-dv/user_extension/user_init.s /home/ali/Documents/ibex/vendor/google_riscv-dv/user_extension/user_define.h /home/ali/Documents/ibex/vendor/google_riscv-dv/files.f /home/ali/Documents/ibex/vendor/google_riscv-dv/requirements.txt /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_vmake /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib2_0.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib2_0.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib4_0.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib4_0.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib1_0.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib3_0.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib3_0.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_dpi/dpi.tfdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib3_0.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib4_0.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib1_0.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib2_0.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib1_0.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/.viscom_cmd_file /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_info /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_lib1_1.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_lib.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_lib1_1.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_lib1_1.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/verilog_style/exclude_filelist.f /home/ali/Documents/ibex/vendor/google_riscv-dv/verilog_style/build-verible.sh /home/ali/Documents/ibex/vendor/google_riscv-dv/verilog_style/run.sh /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/Makefile /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/extension_support.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/handshake.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/index.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/overview.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/generator_flow.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/coverage_model.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/cmd_line_reference.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/getting_started.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/conf.py /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/appendix.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/end_to_end_simulation.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/class_reference.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/trace_csv.png /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/configuration.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/customize_extend_generator.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/make.bat /home/ali/Documents/ibex/vendor/google_riscv-dv/modelsim.ini /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_defines.svh /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_loop_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_signature_pkg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_reg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_vector_cfg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/dv_defines.svh /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_privil_reg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/custom/rv32x_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/custom/rv64x_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/custom/riscv_custom_instr_enum.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/custom/riscv_custom_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32a_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32dc_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32f_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64b_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32b_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64f_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_b_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64c_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32fc_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32m_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_instr_cov.svh /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_compressed_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_amo_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64m_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64a_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_floating_point_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64i_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32d_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv128c_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32c_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64d_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32v_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_vector_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32i_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_cover_group.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_debug_rom_gen.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_stream.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_page_table_entry.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_page_table_exception_cfg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_pseudo_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_callstack_gen.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_page_table.sv riscv_dv_extension/testlist.yaml
rm -rf out/seed-1/instr_gen
python3 /home/ali/Documents/ibex/vendor/google_riscv-dv/run.py \
     --output=out/seed-1/instr_gen  \
     --steps=gen \
     --gen_timeout=1800 \
     --lsf_cmd="" \
     --simulator="questa" \
     --custom_target=riscv_dv_extension --isa="rv32imc" --mabi=ilp32  \
      --start_seed=1 --test="riscv_jump_stress_test" --testlist=riscv_dv_extension/testlist.yaml --iterations=1 \
     --csr_yaml=riscv_dv_extension/csr_description.yaml --isa="rv32imc" --end_signature_addr=8ffffffc \
     --sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,ibex_asm_program_gen,"uvm_test_top.asm_gen" \
                 +signature_addr=8ffffffc +pmp_num_regions=16 \
                 +pmp_granularity=0 +tvec_alignment=8"
Wed, 12 Aug 2020 19:05:27 INFO     Creating output directory: out/seed-1/instr_gen
Wed, 12 Aug 2020 19:05:27 INFO     Processing regression test list : riscv_dv_extension/testlist.yaml, test: riscv_jump_stress_test
Wed, 12 Aug 2020 19:05:28 INFO     Found matched tests: riscv_jump_stress_test, iterations:1
Wed, 12 Aug 2020 19:05:28 INFO     Processing simulator setup file : /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/simulator.yaml
Wed, 12 Aug 2020 19:05:28 INFO     Found matching simulator: questa
Wed, 12 Aug 2020 19:05:28 INFO     Building RISC-V instruction generator
Wed, 12 Aug 2020 19:05:33 INFO     Running RISC-V instruction generator
Wed, 12 Aug 2020 19:05:33 INFO     Generating 1 riscv_jump_stress_test
Wed, 12 Aug 2020 19:05:33 INFO     Running riscv_jump_stress_test with 1 batches
Wed, 12 Aug 2020 19:05:33 INFO     Running riscv_jump_stress_test, batch 1/1, test_cnt:1
touch out/seed-1/.metadata/instr_gen.gen.stamp
Makefile:273: update target 'out/seed-1/.metadata/instr_gen.compile.stamp' due to: out/seed-1/.metadata/instr_gen.gen.stamp riscv_dv_extension/testlist.yaml
python3 /home/ali/Documents/ibex/vendor/google_riscv-dv/run.py \
     --o=out/seed-1/instr_gen  \
     --steps=gcc_compile \
      --start_seed=1 --test="riscv_jump_stress_test" --testlist=riscv_dv_extension/testlist.yaml --iterations=1 \
     --gcc_opts=-mno-strict-align \
     --custom_target=riscv_dv_extension --isa="rv32imc" --mabi=ilp32  && \
  touch out/seed-1/.metadata/instr_gen.compile.stamp
Wed, 12 Aug 2020 19:05:38 INFO     Creating output directory: out/seed-1/instr_gen
Wed, 12 Aug 2020 19:05:38 INFO     Processing regression test list : riscv_dv_extension/testlist.yaml, test: riscv_jump_stress_test
Wed, 12 Aug 2020 19:05:38 INFO     Found matched tests: riscv_jump_stress_test, iterations:1
Wed, 12 Aug 2020 19:05:38 ERROR    Cannot find assembly test: out/seed-1/instr_gen/asm_tests/riscv_jump_stress_test_0.S

make: *** [Makefile:273: out/seed-1/.metadata/instr_gen.compile.stamp] Error 1

Since this log didn't seem to provide more info on the error, I also checked the directory out/seed-1/instr_gen and it looks empty.

also tried using the find command to search for any assembly files in the directory and there doesn't seem to be any found, so it's right to assume that the code gen is failing somewhere.

using make with gen as below:

results in the following, the gen phase seems to end without throwing an error, but there's no assembly file generated in the out directory

Makefile:125: target 'out' does not exist
mkdir -p out
Makefile:142: update target 'out/.sim-cfg.mk' due to: FORCE
./sim_makefrag_gen.py questa experimental-maxperf-pmp-bmfull /home/ali/Documents/ibex out/.sim-cfg.mk
Makefile:125: target 'out/seed-1/.metadata' does not exist
mkdir -p out/seed-1/.metadata
Makefile:247: update target 'out/seed-1/.metadata/instr_gen.gen.stamp' due to: FORCE /home/ali/Documents/ibex/vendor/google_riscv-dv/README.md /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_base_test.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_cov_test.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_test.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_gen_tb_top.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/test/riscv_instr_test_pkg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/setup.cfg /home/ali/Documents/ibex/vendor/google_riscv-dv/design.bin /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/link.ld /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/ovpsim_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/sail_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/deprecated/ovpsim_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/deprecated/spike_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/deprecated/riscv_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/deprecated/instr_trace_compare.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/gen_csr_test.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/ovpsim_log_to_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/riscv_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/instr_trace_compare.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/whisper_log_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/sail_log_to_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/spike_log_to_trace_csv.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/__pycache__/lib.cpython-38.pyc /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/riscv_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/whisper_log_trace_csv.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/instr_trace_compare.py /home/ali/Documents/ibex/vendor/google_riscv-dv/scripts/lib.py /home/ali/Documents/ibex/vendor/google_riscv-dv/run.py /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gcv/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gcv/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gcv/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32i/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32i/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32i/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/multi_harts/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/multi_harts/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/multi_harts/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imcb/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imcb/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imcb/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gc/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gc/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64gc/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imc/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imc/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv64imc/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imc/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imc/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imc/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imcb/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imcb/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/rv32imcb/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/target/ml/riscv_core_setting.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/target/ml/testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/target/ml/riscvOVPsim.ic /home/ali/Documents/ibex/vendor/google_riscv-dv/MANIFEST.in /home/ali/Documents/ibex/vendor/google_riscv-dv/cov.py /home/ali/Documents/ibex/vendor/google_riscv-dv/.flake8 /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_asm_program_gen.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/test/out/.gitkeep /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/test/riscv_instr_base_test.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_defines.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_instr_gen_config.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_instr_sequence.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/target/rv32i/riscv_core_setting.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_instr_pkg.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/isa/rv32i_instr.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_instr.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/pygen_src/riscv_instr_stream.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/README.md /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_asm_program_gen.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/utils.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_instr_sequence.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_callstack_gen.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_rand_instr.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_directed_instr_lib.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_load_store_instr_lib.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_instr_stream.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_data_page_gen.py /home/ali/Documents/ibex/vendor/google_riscv-dv/pygen/experimental/riscv_instr_base.py /home/ali/Documents/ibex/vendor/google_riscv-dv/.gitignore /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/cov_testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/csr_template.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/iss.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/simulator.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/base_testlist.yaml /home/ali/Documents/ibex/vendor/google_riscv-dv/LICENSE.txt /home/ali/Documents/ibex/vendor/google_riscv-dv/.travis.yml /home/ali/Documents/ibex/vendor/google_riscv-dv/questa_sim.tcl /home/ali/Documents/ibex/vendor/google_riscv-dv/qrun_option.f /home/ali/Documents/ibex/vendor/google_riscv-dv/CONTRIBUTING.md /home/ali/Documents/ibex/vendor/google_riscv-dv/riscv.ucdb /home/ali/Documents/ibex/vendor/google_riscv-dv/setup.py /home/ali/Documents/ibex/vendor/google_riscv-dv/vcs.compile.option.f /home/ali/Documents/ibex/vendor/google_riscv-dv/riviera_sim.tcl /home/ali/Documents/ibex/vendor/google_riscv-dv/user_extension/user_extension.svh /home/ali/Documents/ibex/vendor/google_riscv-dv/user_extension/user_init.s /home/ali/Documents/ibex/vendor/google_riscv-dv/user_extension/user_define.h /home/ali/Documents/ibex/vendor/google_riscv-dv/files.f /home/ali/Documents/ibex/vendor/google_riscv-dv/requirements.txt /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_vmake /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib2_0.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib2_0.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib4_0.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib4_0.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib1_0.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib3_0.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib3_0.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_dpi/dpi.tfdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib3_0.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib4_0.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib1_0.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib2_0.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/_lib1_0.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/work/design_opt/.viscom_cmd_file /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_info /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_lib1_1.qpg /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_lib.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_lib1_1.qdb /home/ali/Documents/ibex/vendor/google_riscv-dv/work/_lib1_1.qtl /home/ali/Documents/ibex/vendor/google_riscv-dv/verilog_style/exclude_filelist.f /home/ali/Documents/ibex/vendor/google_riscv-dv/verilog_style/build-verible.sh /home/ali/Documents/ibex/vendor/google_riscv-dv/verilog_style/run.sh /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/Makefile /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/extension_support.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/handshake.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/index.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/overview.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/generator_flow.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/coverage_model.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/cmd_line_reference.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/getting_started.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/conf.py /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/appendix.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/end_to_end_simulation.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/class_reference.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/trace_csv.png /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/configuration.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/source/customize_extend_generator.rst /home/ali/Documents/ibex/vendor/google_riscv-dv/docs/make.bat /home/ali/Documents/ibex/vendor/google_riscv-dv/modelsim.ini /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_defines.svh /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_pmp_cfg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_loop_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_signature_pkg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_reg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_vector_cfg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/dv_defines.svh /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_privil_reg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/custom/rv32x_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/custom/rv64x_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/custom/riscv_custom_instr_enum.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/custom/riscv_custom_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32a_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32dc_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32f_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64b_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32b_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64f_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_b_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64c_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32fc_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32m_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_instr_cov.svh /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_compressed_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_amo_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64m_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64a_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_floating_point_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64i_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32d_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv128c_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32c_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv64d_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32v_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_vector_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/riscv_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/isa/rv32i_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_cover_group.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_debug_rom_gen.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_stream.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_page_table_entry.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_page_table_exception_cfg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_pseudo_instr.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_callstack_gen.sv /home/ali/Documents/ibex/vendor/google_riscv-dv/src/riscv_page_table.sv riscv_dv_extension/testlist.yaml
rm -rf out/seed-1/instr_gen
python3 /home/ali/Documents/ibex/vendor/google_riscv-dv/run.py \
     --output=out/seed-1/instr_gen  \
     --steps=gen \
     --gen_timeout=1800 \
     --lsf_cmd="" \
     --simulator="questa" \
     --custom_target=riscv_dv_extension --isa="rv32imc" --mabi=ilp32  \
      --start_seed=1 --test="riscv_jump_stress_test" --testlist=riscv_dv_extension/testlist.yaml --iterations=1 \
     --csr_yaml=riscv_dv_extension/csr_description.yaml --isa="rv32imc" --end_signature_addr=8ffffffc \
     --sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,ibex_asm_program_gen,"uvm_test_top.asm_gen" \
                 +signature_addr=8ffffffc +pmp_num_regions=16 \
                 +pmp_granularity=0 +tvec_alignment=8"
Wed, 12 Aug 2020 19:14:35 INFO     Creating output directory: out/seed-1/instr_gen
Wed, 12 Aug 2020 19:14:35 INFO     Processing regression test list : riscv_dv_extension/testlist.yaml, test: riscv_jump_stress_test
Wed, 12 Aug 2020 19:14:35 INFO     Found matched tests: riscv_jump_stress_test, iterations:1
Wed, 12 Aug 2020 19:14:35 INFO     Processing simulator setup file : /home/ali/Documents/ibex/vendor/google_riscv-dv/yaml/simulator.yaml
Wed, 12 Aug 2020 19:14:35 INFO     Found matching simulator: questa
Wed, 12 Aug 2020 19:14:35 INFO     Building RISC-V instruction generator
Wed, 12 Aug 2020 19:14:40 INFO     Running RISC-V instruction generator
Wed, 12 Aug 2020 19:14:40 INFO     Generating 1 riscv_jump_stress_test
Wed, 12 Aug 2020 19:14:40 INFO     Running riscv_jump_stress_test with 1 batches
Wed, 12 Aug 2020 19:14:40 INFO     Running riscv_jump_stress_test, batch 1/1, test_cnt:1
touch out/seed-1/.metadata/instr_gen.gen.stamp

I understand you guys use VCS, I am happy help debugging the issue for Questa.

rswarbrick commented 4 years ago

Hmm, that's frustrating. Well, there aren't any magic environment variables set in the Makefile, so you should be able to run the run.py command above on its own. If you do so, you can add a -v flag that turns on "verbose mode". This should give you the Questa command that's actually running, as well as any log output that it generates.

Squinting at the log above, I think you can run:

python3 /home/ali/Documents/ibex/vendor/google_riscv-dv/run.py \
     --output=out/seed-1/instr_gen  \
     --steps=gen \
     --gen_timeout=1800 \
     --lsf_cmd="" \
     --simulator="questa" \
     --custom_target=riscv_dv_extension --isa="rv32imc" --mabi=ilp32  \
      --start_seed=1 --test="riscv_jump_stress_test" --testlist=riscv_dv_extension/testlist.yaml --iterations=1 \
     --csr_yaml=riscv_dv_extension/csr_description.yaml --isa="rv32imc" --end_signature_addr=8ffffffc \
     --sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,ibex_asm_program_gen,"uvm_test_top.asm_gen" \
                 +signature_addr=8ffffffc +pmp_num_regions=16 \
                 +pmp_granularity=0 +tvec_alignment=8" \
     -v
udinator commented 4 years ago

Hi @aliess - to add on to what @rswarbrick is suggesting, if the instruction generation still doesn't seem to be working after trying to run the run.py command by itself to generate/compile the assembly file, can you please file a duplicate of this issue in https://github.com/google/riscv-dv? One of our contributors is very familiar with Questa and might be able to provide some more advice (we primarily use VCS to develop the instruction generator).

aliess commented 4 years ago

I cloned https://github.com/google/riscv-dv and I have the same issue there so I opened an issue there.

rswarbrick commented 4 years ago

Great, thanks!

imphil commented 3 years ago

Assuming this is/will be addressed in riscv-dv.

Shaileshkavar commented 1 year ago

Hello,

When I am trying to run UVM tests, using the below command to generate riscv_arithmetic_basic_testfor example:

make instr_gen_run SIMULATOR=questa TEST=riscv_arithmetic_basic_test ISS=spike ISA=rv32imc SEED=1 ISA=rv32imc

Error:

placeholder_dir /tmp/tmps1r1tvid/@@PLACEHOLDER@@ build_dir /users3/shailesh.kavar/riscv-ibex/ibex/dv/uvm/core_ibex/out/build/instr_gen placeholder_dir /tmp/tmps1r1tvid/@@PLACEHOLDER@@ build_dir /users3/shailesh.kavar/riscv-ibex/ibex/dv/uvm/core_ibex/out/build/instr_gen file_copies [('gen.log', 'gen.log', True), ('test_0.S', 'test.S', False)] src_path: /tmp/tmps1r1tvid/gen.log dst_path: /users3/shailesh.kavar/riscv-ibex/ibex/dv/uvm/core_ibex/out/run/tests/riscv_arithmetic_basic_test.1/gen.log Compiling generated test assembly to create binary at out/run/tests/riscv_arithmetic_basic_test.1/test.bin cc1: fatal error: /users3/shailesh.kavar/riscv-ibex/ibex/dv/uvm/core_ibex/out/run/tests/riscv_arithmetic_basic_test.1/test.S: No such file or directory compilation terminated.

And when I tried to generate the assembly file for the same test in google-riscv, it is generated properly.

[shailesh.kavar@vnc12 ~/riscv-ibex/ibex/vendor/google_riscv-dv]% python3 run.py --test riscv_arithmetic_basic_test --simulator questa Fri, 25 Nov 2022 11:18:49 INFO Creating output directory: out_2022-11-25 Fri, 25 Nov 2022 11:18:49 INFO Processing regression test list : /users3/shailesh.kavar/riscv-ibex/ibex/vendor/google_riscv-dv/target/rv32imc/testlist.yaml, test: riscv_arithmetic_basic_test Fri, 25 Nov 2022 11:18:49 INFO Processing regression test list : /users3/shailesh.kavar/riscv-ibex/ibex/vendor/google_riscv-dv/yaml/base_testlist.yaml, test: riscv_arithmetic_basic_test Fri, 25 Nov 2022 11:18:49 INFO Found matched tests: riscv_arithmetic_basic_test, iterations:2 Fri, 25 Nov 2022 11:18:49 INFO Processing simulator setup file : /users3/shailesh.kavar/riscv-ibex/ibex/vendor/google_riscv-dv/yaml/simulator.yaml Fri, 25 Nov 2022 11:18:49 INFO Found matching simulator: questa Fri, 25 Nov 2022 11:18:49 INFO Building RISC-V instruction generator Fri, 25 Nov 2022 11:19:04 INFO Running RISC-V instruction generator Fri, 25 Nov 2022 11:19:04 INFO Generating 2 riscv_arithmetic_basic_test Fri, 25 Nov 2022 11:19:04 INFO Running riscv_arithmetic_basic_test with 1 batches Fri, 25 Nov 2022 11:19:04 INFO Running riscv_arithmetic_basic_test, batch 1/1, test_cnt:2 Fri, 25 Nov 2022 11:19:16 INFO Compiling out_2022-11-25/asm_test/riscv_arithmetic_basic_test_0.S Fri, 25 Nov 2022 11:19:16 INFO Converting to out_2022-11-25/asm_test/riscv_arithmetic_basic_test_0.bin Fri, 25 Nov 2022 11:19:16 INFO Compiling out_2022-11-25/asm_test/riscv_arithmetic_basic_test_1.S Fri, 25 Nov 2022 11:19:16 INFO Converting to out_2022-11-25/asm_test/riscv_arithmetic_basic_test_1.bin Fri, 25 Nov 2022 11:19:16 INFO Processing ISS setup file : /users3/shailesh.kavar/riscv-ibex/ibex/vendor/google_riscv-dv/yaml/iss.yaml