search

lowRISC / ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
https://www.lowrisc.org
Apache License 2.0
1.37k stars 541 forks source link

[ci] Let's try to integrate a Yosys synthesis flow into CI #1481

Open rswarbrick opened 2 years ago

rswarbrick commented 2 years ago

The guys at Antmicro have been working on their Surelog+UHDM+Yosys flow and it seems that it can now build Ibex with vanilla Yosys plus their stuff as a plugin.

It would be neat if we could try running this in CI. We'd get early warning if we made a change that broke their frontend (possibly a sign of a genuine Verilog error) and we'd also get instant kGE estimates.

We'll need to decide which version of the software to track and how to "install" it. Maybe the right approach would be for Antmicro to generate a docker image containing the tool, so we could consume that?

We'll also need to figure out how to run stuff. A GitHub action? Some sort of Azure integration?

rswarbrick commented 2 years ago

@tgorochowik: Please correct me if I've mangled something here! :-)

tgorochowik commented 2 years ago

Sure, thanks! If you want to go with the docker image approach we could create an action (similar to the action with verible) and use it. This way it should be possible to control the version of yosys/uhdm plugin we're using. We're of course open to doing it differently too (be it compiling everything in the CI or providing binaries in some way). Thanks again!

johngt commented 2 years ago

I believe that this effort is still ongoing but will likely not make it before V2, so bringing it into the Project to be tracked as a future effort.

GregAC commented 2 years ago

Removed from DV project as this is not DV related