Why performance counters don’t start counting right away

[Liyang131313]

Hello, I would like to ask, why the program has been executed for a while during the simulation process, and the performance counters will start working. Instead of starting work immediately during system startup. Is it because the firmware code is being executed? Does the performance counter work require firmware? If the firmware code is not executing, what is the operation, causing the performance counters to not start working immediately?

@zarubaf @Razer6 @wallento

[vogelpi]

Hi @Liyang131313 , the behavior of the performance counters PCCR_q[0] - PCCR_q[10] are controlled by the two registers:

• PCER: the performance counter enable register has one bit per counter to decide if that particular counter is enabled (1) or disabled (0). This register is mapped to TSELECT @ CSR 0x7a0.

• PCMR: the performance counter mode select register has two bits

  • Bit 0 globally enables (1) or disables (0) all performance counters,
  • Bit 1 globally controls whether the counters should saturate (1) or overflow (0).

  The PCMR is mapped to TDATA1 @ CSR 0x7a1.

After a reset, all counters are disabled (PCER = '0, but PCMR = 2'h3). Your program first writes 2 to the PCER meaning the instruction counter in PCER_q[1] is enabled. In addition, your program is writing 3 to the PCMR.

Consequently, only PCER_q[1], i.e., the instruction counter, should be active, which is what you can see in the traces.

Best regards, Pirmin