CSR_SCONTEXT, CSR_MCONTEXT, CSR_TDATA3 are also the ignored CSRs, remove this coverpoint?
Justification
None of these is particularly complex but it's all small changes to spike that add up.
CSR_SCONTEXT / CSR_MCONTEXT are optional CSRs only accessible in debug mode, Ibex implements them as read as 0, write ignore. They do not need to implemented and aren't used by our debug setup. As they're not accessible via debug mode this is a low priority item to test
CSR_MSECCFGH/CSR_MENVCFGH - These CSRs have no implemented bits and are only accessible in M mode. They're in the M mode only CSR space so the generic check that accesses from U mode cause illegal instruction exceptions is sufficiently testing by other illegal CSR accesses from U mode.
CSR_TDATA3 - This is accessible in M mode and is an optional CSR for debug trigger points, Ibex implements it as read as 0 write ignore.
CSR_MCOUNTINHIBIT - The controls the performance counters and is not a high priority item.
Coverpoints/bins affected
cp_csr_read_only
/cp_csr_write
CSR_SCONTEXT
CSR_MCONTEXT
CSR_MSECCFGH
CSR_TDATA3
CSR_MCOUNTINHIBIT
CSR_MENVCFGH
cp_ignored_csrs
/cp_ignored_csrs_w
CSR_SCONTEXT
,CSR_MCONTEXT
,CSR_TDATA3
are also the ignored CSRs, remove this coverpoint?Justification
None of these is particularly complex but it's all small changes to spike that add up.
CSR_SCONTEXT
/CSR_MCONTEXT
are optional CSRs only accessible in debug mode, Ibex implements them as read as 0, write ignore. They do not need to implemented and aren't used by our debug setup. As they're not accessible via debug mode this is a low priority item to testCSR_MSECCFGH
/CSR_MENVCFGH
- These CSRs have no implemented bits and are only accessible in M mode. They're in the M mode only CSR space so the generic check that accesses from U mode cause illegal instruction exceptions is sufficiently testing by other illegal CSR accesses from U mode.CSR_TDATA3
- This is accessible in M mode and is an optional CSR for debug trigger points, Ibex implements it as read as 0 write ignore.CSR_MCOUNTINHIBIT
- The controls the performance counters and is not a high priority item.