lowRISC / ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
https://www.lowrisc.org
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[dv] CSR Coverage Waiver #1795

Open GregAC opened 2 years ago

GregAC commented 2 years ago

Coverpoints/bins affected

Justification

None of these is particularly complex but it's all small changes to spike that add up.

CSR_SCONTEXT / CSR_MCONTEXT are optional CSRs only accessible in debug mode, Ibex implements them as read as 0, write ignore. They do not need to implemented and aren't used by our debug setup. As they're not accessible via debug mode this is a low priority item to test

CSR_MSECCFGH/CSR_MENVCFGH - These CSRs have no implemented bits and are only accessible in M mode. They're in the M mode only CSR space so the generic check that accesses from U mode cause illegal instruction exceptions is sufficiently testing by other illegal CSR accesses from U mode.

CSR_TDATA3 - This is accessible in M mode and is an optional CSR for debug trigger points, Ibex implements it as read as 0 write ignore.

CSR_MCOUNTINHIBIT - The controls the performance counters and is not a high priority item.

estimate 4

GregAC commented 1 year ago

We should consider stimulating these for V3

GregAC commented 1 year ago

I think at least some of this has been addressed, need to revisit.

GregAC commented 1 year ago

estimate range: 2 - 4