SimpleSystem cannot be simulated using xcelium

ZeroSebastian commented 1 year ago

Observed Behavior

The xrun command fails with:

$ make run
/home/eda/cadence/XCELIUM/XCELIUM2209/tools/bin/xrun -q -f edalize_main.f    -defparam RV32E=0 -defparam ICache=0 -defparam ICacheScramble=0 -defparam ICacheECC=0 -defparam BranchTargetALU=0 -defparam WritebackStage=0 -defparam SecureIbex=0 -defparam BranchPredictor=0 -defparam DbgTriggerEn=0 -defparam PMPEnable=0 -defparam PMPGranularity=0 -defparam PMPNumRegions=4 -defparam MHPMCounterNum=0 -defparam MHPMCounterWidth=40 -defparam SRAMInitFile=  -top ibex_simple_system
  `DV_FCOV_SIGNAL_GEN_IF(logic [1:0], dummy_instr_type,
                       |
xmvlog: *E,NOTDIR (../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_if_stage.sv,690|23): `DV_FCOV_SIGNAL_GEN_IF: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
  `DV_FCOV_SIGNAL_GEN_IF(logic [1:0], dummy_instr_type,
                        |
xmvlog: *E,EXPENM (../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_if_stage.sv,690|24): expecting the keyword 'endmodule' [12.1(IEEE)].
  `DV_FCOV_SIGNAL_GEN_IF(logic, insert_dummy_instr,
                       |
xmvlog: *E,NOTDIR (../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_if_stage.sv,692|23): `DV_FCOV_SIGNAL_GEN_IF: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
xrun: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 1).
make: *** [run] Error 1

Expected Behavior

Starting a simulation with SimpleSystem in Xcelium

Steps to reproduce the issue

First i executed the fusesoc command: fusesoc --cores-root=. run --target=sim --tool=xcelium --setup --build lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast --SRAMInitFile=./examples/sw/simple_system/hello_test/hello_test.vmem``

since the usage of network is restricted on my machine where I can use the xcelium simulator (fusesoc is not installed there), I copied the whole build folder from the root repository to that machine and executed make run in ./build/lowrisc_ibex_ibex_simple_system_0/sim-xcelium

I use the unmodified ibex source code, I just want to set up a initial setup. I also looked into the Makefiles and the directory that includes the header where the missing macro is defined is included. What am I missing here?

My Environment

EDA tool and version:

Cadence XCelium 22.09.s006

Operating system:

CentOS Linux 7 (Core)

Version of the Ibex source code:

latest master branch 93c8e92

GregAC commented 1 year ago

We tend to run simple system using Verilator so it's possible it's currently broken on Xcelium.

DV_FCOV_SIGNAL_GEN_IF is a macro defined here: https://github.com/lowRISC/ibex/blob/master/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh I note that dv_fcov_macros.svh should be included in files that use it but it isn't included in ibex_if_stage.sv. This hasn't caused us issues thus far (in particular our Xcelium DV runs) but we should have the include so I've fixed this here: https://github.com/lowRISC/ibex/pull/2007

ZeroSebastian commented 1 year ago

Thank you, I just added the same changes to my working copy and this fixes it for now (since the changes have not yet been merged).

lowRISC / ibex